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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dqcom,sm8650-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8650 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8650 SoC.
20 - const: qcom,sm8650-lpass-lpi-pinctrl
22 - const: qcom,sm8750-lpass-lpi-pinctrl
23 - const: qcom,sm8650-lpass-lpi-pinctrl
27 - description: LPASS LPI TLMM Control and Status registers
54 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
79 - $ref: qcom,lpass-lpi-common.yaml#
94 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
H A Dqcom,sm4250-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM4250 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC.
18 const: qcom,sm4250-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
48 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
72 - $ref: qcom,lpass-lpi-common.yaml#
86 compatible = "qcom,sm4250-lpass-lpi-pinctrl";
H A Dqcom,sc8280xp-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SC8280XP SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SC8280XP SoC.
18 const: qcom,sc8280xp-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
74 - $ref: qcom,lpass-lpi-common.yaml#
88 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
H A Dqcom,sm8550-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8550 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC.
20 - const: qcom,sm8550-lpass-lpi-pinctrl
22 - const: qcom,x1e80100-lpass-lpi-pinctrl
23 - const: qcom,sm8550-lpass-lpi-pinctrl
27 - description: LPASS LPI TLMM Control and Status registers
28 - description: LPASS LPI MCC registers
55 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
80 - $ref: qcom,lpass-lpi
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H A Dqcom,sm8450-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8450 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
18 const: qcom,sm8450-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
76 - $ref: qcom,lpass-lpi-common.yaml#
90 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
H A Dqcom,lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
8 Low Power Island (LPI) TLMM block
15 LPASS LPI IP on most Qualcomm SoCs
19 const: qcom,sm8250-lpass-lpi-pinctrl
124 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
H A Dqcom,sc7280-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SC7280 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SC7280 SoC.
18 const: qcom,sc7280-lpass-lpi-pinctrl
38 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
67 - $ref: qcom,lpass-lpi-common.yaml#
74 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
H A Dqcom,sm8250-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8250 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.
18 const: qcom,sm8250-lpass-lpi-pinctrl
48 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
73 - $ref: qcom,lpass-lpi-common.yaml#
87 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DSjLjEHPrepare.cpp65 void substituteLPadValues(LandingPadInst *LPI, Value *ExnVal, Value *SelVal);
158 void SjLjEHPrepareImpl::substituteLPadValues(LandingPadInst *LPI, Value *ExnVal, in substituteLPadValues() argument
160 SmallVector<Value *, 8> UseWorkList(LPI->users()); in substituteLPadValues()
176 if (LPI->use_empty()) in substituteLPadValues()
179 // There are still some uses of LPI. Construct an aggregate with the exception in substituteLPadValues()
180 // values and replace the LPI with that aggregate. in substituteLPadValues()
181 Type *LPadType = LPI->getType(); in substituteLPadValues()
188 LPI->replaceAllUsesWith(LPadVal); in substituteLPadValues()
207 for (LandingPadInst *LPI : LPads) { in setupFunctionContext()
208 IRBuilder<> Builder(LPI->getParent(), in setupFunctionContext()
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/freebsd/sys/arm64/arm64/
H A Dgicv5_its.c217 /* LPI chunk owned by ITS device */
220 u_int lpi_free; /* First free LPI in set */
902 u_int event_id, u_int lpi) in gicv5_its_alloc_irqsrc() argument
906 KASSERT(sc->sc_irqs[lpi] == NULL, in gicv5_its_alloc_irqsrc()
907 ("%s: LPI %u already allocated", __func__, lpi)); in gicv5_its_alloc_irqsrc()
922 "%s,%u", device_get_nameunit(dev), lpi) != 0) { in gicv5_its_alloc_irqsrc()
928 gicv5_irs_extend_ist(device_get_parent(dev), dev, lpi); in gicv5_its_alloc_irqsrc()
930 girq->gi_isrc.gbi_irq = lpi; in gicv5_its_alloc_irqsrc()
932 sc->sc_irqs[lpi] = girq; in gicv5_its_alloc_irqsrc()
984 u_int event_id, lpi; in gicv5_its_alloc_msi() local
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H A Dgicv5.c70 #define LPI_IS_IPI(lpi) ((lpi) < LPI_ITS_BASE) argument
71 #define LPI_IPI_IDX(lpi) ((lpi) - LPI_IPI_BASE) argument
72 #define LPI_TO_IPI(lpi) (LPI_IPI_IDX(lpi) % INTR_IPI_COUNT) argument
316 gicv5_irs_extend_ist(device_t dev, device_t child, u_int lpi) in gicv5_irs_extend_ist() argument
337 index = lpi >> irs->irs_lpi_l2bits; in gicv5_irs_extend_ist()
367 IRS_CFG_WRITE_4(irs, IRS_MAP_L2_ISTR, lpi); in gicv5_irs_extend_ist()
680 panic("%s: Unable to register LPI irq src", in gicv5_attach()
919 ("%s: Invalid IPI LPI %u", __func__, irq)); in gicv5_intr()
925 "IPI LPI %u on UP system detected\n", ipi); in gicv5_intr()
1097 * 2 = LPI in gic_map_fdt()
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H A Dgic_v3_reg.h41 /* Upper value is determined by LPI max priority */
186 * The PROPBASER LPI Configuration Table is 4k aligned, so bits 51:12 are
238 * The LPI Pending Table (PENDBASER) is 64k aligned. So bits 51:16 are defined to be the PA, for 36
458 * LPI related
H A Dgicv3_its.c100 /* 1 bit per SPI, PPI, and SGI (8k), and 1 bit per LPI (LPI_CONFTAB_SIZE) */
124 /* Virtual LPI ID */
126 /* Physical LPI ID */
142 /* LPI chunk owned by ITS device */
145 u_int lpi_free; /* First free LPI in set */
771 panic("Cannot map prior LPI mapping into KVA"); in gicv3_its_conftable_init()
775 "LPI enabled, conf table using pa %#lx va %p\n", in gicv3_its_conftable_init()
834 * don't need to disable / enable LPI if we're not changing PROPBASER, in its_init_cpu_lpi()
879 * Set the LPI pending table base in its_init_cpu_lpi()
948 /* Do per-cpu LPI init once */ in its_init_cpu()
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/freebsd/sys/dev/neta/
H A Dif_mvnetareg.h224 #define MVNETA_LPIC1 0x2cc4 /* LPI control 1 */
225 #define MVNETA_LPIC2 0x2cc8 /* LPI control 2 */
226 #define MVNETA_LPIS 0x2ccc /* LPI status */
227 #define MVNETA_LPIC 0x2cd0 /* LPI counter */
670 #define MVNETA_PI_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/
671 #define MVNETA_PI_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/
672 #define MVNETA_PI_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/
678 /* LPI Control 0 (MVNETA_LPIC0) */
682 /* LPI Control 1 (MVNETA_LPIC1) */
683 #define MVNETA_LPIC1_LPIRE (1 << 0) /* LPI request enable */
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsnps,dwc-qos-ethernet.txt108 - snps,en-lpi: If present it enables use of the AXI low-power interface
117 - snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
149 snps,en-tx-lpi-clockgating;
150 snps,en-lpi;
H A Dsamsung-sxgbe.txt8 transmit DMA interrupts, receive DMA interrupts and lpi interrupt.
12 and 1 optional lpi interrupt.
H A Dqcom,ethqos.yaml49 - description: The interrupt that occurs when Rx exits the LPI state
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm4250.dtsi41 compatible = "qcom,sm4250-lpass-lpi-pinctrl";
44 lpi_i2s2_active: lpi-i2s2-active-state {
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dqcom,sm6115-pas.yaml107 - description: LPI CX power domain
108 - description: LPI MX power domain
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DEHStreamer.cpp94 for (const LandingPadInfo *LPI : LandingPads) { in computeActionsTable() local
95 const std::vector<int> &TypeIds = LPI->TypeIds; in computeActionsTable()
96 unsigned NumShared = PrevLPI ? sharedTypeIDs(LPI, PrevLPI) : 0; in computeActionsTable()
150 PrevLPI = LPI; in computeActionsTable()
390 for (const LandingPadInfo &LPI : PadInfos) { in emitExceptionTable() local
394 if (LPI.LandingPadLabel && !LPI.LandingPadLabel->isDefined()) in emitExceptionTable()
396 LandingPads.push_back(&LPI); in emitExceptionTable()
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic-v5.yaml27 - Logical Peripheral Interrupts (LPI)
47 3 for SPI. LPI interrupts must not be described in the bindings since
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Dpower.h547 * @IWL_PPAG_ETSI_LPI_UHB_MASK: enable LPI in ETSI for UHB
550 * @IWL_PPAG_USA_LPI_UHB_MASK: enable LPI in USA for UHB
553 * @IWL_PPAG_CANADA_LPI_UHB_MASK: enable LPI in CANADA for UHB
767 * Used for VLP/LPI/AFC Access Point power constraints for 6GHz channels
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerEmscriptenEHSjLj.cpp1205 if (auto *LPI = dyn_cast<LandingPadInst>(I)) in runEHOnFunction() local
1206 LandingPads.insert(LPI); in runEHOnFunction()
1212 for (LandingPadInst *LPI : LandingPads) { in runEHOnFunction()
1213 IRB.SetInsertPoint(LPI); in runEHOnFunction()
1215 for (unsigned I = 0, E = LPI->getNumClauses(); I < E; ++I) { in runEHOnFunction()
1216 Constant *Clause = LPI->getClause(I); in runEHOnFunction()
1219 if (LPI->isCatch(I)) in runEHOnFunction()
1226 Value *Poison = PoisonValue::get(LPI->getType()); in runEHOnFunction()
1231 LPI->replaceAllUsesWith(Pair1); in runEHOnFunction()
1232 ToErase.push_back(LPI); in runEHOnFunction()
/freebsd/sys/dev/igc/
H A Digc_defines.h805 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
806 #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
810 #define IGC_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
811 #define IGC_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
829 #define IGC_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
1279 * of EEE LPI Tx state
1283 * of EEE LPI Tx state
/freebsd/sys/dev/e1000/
H A De1000_ich8lan.h284 #define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */
291 #define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */

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