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/linux/drivers/acpi/riscv/
H A Dcpuidle.c25 struct acpi_lpi_state *lpi; in acpi_cpu_init_idle() local
40 lpi = &pr->power.lpi_states[i]; in acpi_cpu_init_idle()
48 if (((lpi->address & RISCV_FFH_LPI_TYPE_MASK) != RISCV_FFH_LPI_TYPE_SBI) || in acpi_cpu_init_idle()
49 (lpi->address & RISCV_FFH_LPI_RSVD_MASK)) { in acpi_cpu_init_idle()
50 pr_warn("Invalid LPI entry method %#llx\n", lpi->address); in acpi_cpu_init_idle()
54 state = lpi->address; in acpi_cpu_init_idle()
69 int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) in acpi_processor_ffh_lpi_enter() argument
71 u32 state = lpi->address; in acpi_processor_ffh_lpi_enter()
75 lpi->index, in acpi_processor_ffh_lpi_enter()
79 lpi->index, in acpi_processor_ffh_lpi_enter()
/linux/drivers/acpi/arm64/
H A Dcpuidle.c20 struct acpi_lpi_state *lpi; in psci_acpi_cpu_init_idle() local
40 lpi = &pr->power.lpi_states[i + 1]; in psci_acpi_cpu_init_idle()
45 state = lpi->address; in psci_acpi_cpu_init_idle()
60 __cpuidle int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) in acpi_processor_ffh_lpi_enter() argument
62 u32 state = lpi->address; in acpi_processor_ffh_lpi_enter()
64 if (ARM64_LPI_IS_RETENTION_STATE(lpi->arch_flags)) in acpi_processor_ffh_lpi_enter()
66 lpi->index, state); in acpi_processor_ffh_lpi_enter()
69 lpi->index, state); in acpi_processor_ffh_lpi_enter()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm4250-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM4250 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC.
18 const: qcom,sm4250-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
48 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
72 - $ref: qcom,lpass-lpi-common.yaml#
86 compatible = "qcom,sm4250-lpass-lpi-pinctrl";
H A Dqcom,sc8280xp-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SC8280XP SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SC8280XP SoC.
18 const: qcom,sc8280xp-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
74 - $ref: qcom,lpass-lpi-common.yaml#
88 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
H A Dqcom,sm8450-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8450 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
18 const: qcom,sm8450-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
76 - $ref: qcom,lpass-lpi-common.yaml#
90 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
H A Dqcom,sm8250-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8250 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.
18 const: qcom,sm8250-lpass-lpi-pinctrl
48 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
73 - $ref: qcom,lpass-lpi-common.yaml#
87 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_core.c53 /* Reading this register shall clear all the LPI status bits */ in sxgbe_get_lpi_status()
190 /* Enable the LPI mode for transmit path with Tx automate bit set. in sxgbe_set_eee_mode()
192 * to LPI mode after all outstanding and pending packets are in sxgbe_set_eee_mode()
229 /* Program the timers in the LPI timer control register: in sxgbe_set_eee_timer()
232 * the LPI pattern. in sxgbe_set_eee_timer()
234 * after it has stopped transmitting the LPI pattern. in sxgbe_set_eee_timer()
H A Dsxgbe_common.h118 /* EEE-LPI mode flags*/
124 /* EEE-LPI Interrupt status flag */
127 /* EEE-LPI Default timer values */
131 /* EEE-LPI Control and status definitions */
243 /* EEE-LPI stats */
348 /* EEE-LPI specific operations */
501 /* EEE-LPI specific members */
/linux/drivers/pinctrl/qcom/
H A Dpinctrl-sm8250-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
130 .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
139 .name = "qcom-sm8250-lpass-lpi-pinctrl",
147 MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
H A Dpinctrl-sc7280-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
132 .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
141 .name = "qcom-sc7280-lpass-lpi-pinctrl",
149 MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
H A Dpinctrl-sm6115-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
139 { .compatible = "qcom,sm6115-lpass-lpi-pinctrl", .data = &sm6115_lpi_data },
146 .name = "qcom-sm6115-lpass-lpi-pinctrl",
154 MODULE_DESCRIPTION("QTI SM6115 LPI GPIO pin control driver");
H A Dpinctrl-sm8350-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
132 .compatible = "qcom,sm8350-lpass-lpi-pinctrl",
141 .name = "qcom-sm8350-lpass-lpi-pinctrl",
150 MODULE_DESCRIPTION("QTI SM8350 LPI GPIO pin control driver");
H A Dpinctrl-sc8280xp-lpass-lpi.c10 #include "pinctrl-lpass-lpi.h"
169 .compatible = "qcom,sc8280xp-lpass-lpi-pinctrl",
178 .name = "qcom-sc8280xp-lpass-lpi-pinctrl",
186 MODULE_DESCRIPTION("QTI SC8280XP LPI GPIO pin control driver");
H A Dpinctrl-sm8450-lpass-lpi.c10 #include "pinctrl-lpass-lpi.h"
198 .compatible = "qcom,sm8450-lpass-lpi-pinctrl",
207 .name = "qcom-sm8450-lpass-lpi-pinctrl",
215 MODULE_DESCRIPTION("QTI SM8450 LPI GPIO pin control driver");
H A Dpinctrl-sm8550-lpass-lpi.c10 #include "pinctrl-lpass-lpi.h"
206 .compatible = "qcom,sm8550-lpass-lpi-pinctrl",
215 .name = "qcom-sm8550-lpass-lpi-pinctrl",
223 MODULE_DESCRIPTION("Qualcomm SM8550 LPI GPIO pin control driver");
H A Dpinctrl-sm8650-lpass-lpi.c10 #include "pinctrl-lpass-lpi.h"
213 .compatible = "qcom,sm8650-lpass-lpi-pinctrl",
222 .name = "qcom-sm8650-lpass-lpi-pinctrl",
230 MODULE_DESCRIPTION("Qualcomm SM8650 LPI GPIO pin control driver");
H A Dpinctrl-sm4250-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
219 { .compatible = "qcom,sm4250-lpass-lpi-pinctrl", .data = &sm4250_lpi_data },
226 .name = "qcom-sm4250-lpass-lpi-pinctrl",
234 MODULE_DESCRIPTION("QTI SM4250 LPI GPIO pin control driver");
/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt108 - snps,en-lpi: If present it enables use of the AXI low-power interface
117 - snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
149 snps,en-tx-lpi-clockgating;
150 snps,en-lpi;
H A Dsamsung-sxgbe.txt8 transmit DMA interrupts, receive DMA interrupts and lpi interrupt.
12 and 1 optional lpi interrupt.
/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst173 This parameter changes the default LPI TX Expiration time in milliseconds.
295 family of Physical layer to operate in the Low Power Idle (LPI) mode. The EEE
298 The LPI mode allows power saving by switching off parts of the communication
302 the system should enter or exit the LPI mode and communicate this to PHY.
308 To enter in TX LPI mode the driver needs to have a software timer that enable
309 and disable the LPI mode when there is nothing to be transmitted.
490 35) Enables TX LPI Clock Gating::
570 1) Enable AXI LPI::
/linux/drivers/irqchip/
H A Dirq-gic-v5-its.c844 static int gicv5_its_map_event(struct gicv5_its_dev *its_dev, u16 event_id, u32 lpi) in gicv5_its_map_event() argument
855 itt_entry = FIELD_PREP(GICV5_ITTL2E_LPI_ID, lpi) | in gicv5_its_map_event()
930 u32 device_id, event_id_base, lpi; in gicv5_its_irq_domain_alloc() local
952 pr_debug("Failed to find free LPI!\n"); in gicv5_its_irq_domain_alloc()
955 lpi = ret; in gicv5_its_irq_domain_alloc()
957 ret = irq_domain_alloc_irqs_parent(domain, virq + i, 1, &lpi); in gicv5_its_irq_domain_alloc()
959 gicv5_free_lpi(lpi); in gicv5_its_irq_domain_alloc()
1028 u32 lpi; in gicv5_its_irq_domain_activate() local
1031 lpi = d->parent_data->hwirq; in gicv5_its_irq_domain_activate()
1033 return gicv5_its_map_event(its_dev, event_id, lpi); in gicv5_its_irq_domain_activate()
H A Dirq-gic-v4.c32 * physical LPI which gets unmapped when the guest maps the
34 * mapped to the LPI (host) or the VLPI (guest). Note that this is
66 * dialect) gets a single doorbell LPI, no matter how many interrupts
73 * turn, this domain sits on top of the normal LPI allocator, and a
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac4_core.c45 /* Configure LPI 1us counter to number of CSR clock ticks in 1us - 1 */ in dwmac4_core_init()
399 /* Set the hardware LPI entry timer */ in dwmac4_set_lpi_mode()
402 /* Interpret a zero LPI entry timer to mean in dwmac4_set_lpi_mode()
403 * immediate entry into LPI mode. in dwmac4_set_lpi_mode()
442 /* Program the timers in the LPI timer control register: in dwmac4_set_eee_timer()
445 * the LPI pattern. in dwmac4_set_eee_timer()
447 * after it has stopped transmitting the LPI pattern. in dwmac4_set_eee_timer()
642 /* MAC tx/rx EEE LPI entry/exit interrupts */ in dwmac4_irq_mtl_status()
644 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */ in dwmac4_irq_mtl_status()
/linux/arch/arm64/kvm/vgic/
H A Dvgic-its.c70 * Creates a new (reference to a) struct vgic_irq for a given LPI.
71 * If this LPI is already mapped on another ITS, we increase its refcount
73 * If this is a "new" LPI, we allocate and initialize a new struct vgic_irq.
111 * check that we don't add a second list entry with the same LPI. in vgic_add_lpi()
115 /* Someone was faster with adding this LPI, lets use that. */ in vgic_add_lpi()
134 * the respective config data from memory here upon mapping the LPI. in vgic_add_lpi()
136 * Should any of these fail, behave as if we couldn't create the LPI in vgic_add_lpi()
275 * Reads the configuration data for a given LPI from guest memory and
343 * Promotes the ITS view of affinity of an ITTE (which redistributor this LPI
360 * Updates the target VCPU for every LPI targeting this collection.
[all …]
/linux/drivers/net/pcs/
H A Dpcs-xpcs.h82 #define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */
83 #define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */

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