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/freebsd/sys/contrib/device-tree/Bindings/ddr/
H A Dlpddr2.txt1 * LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
4 - compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
5 "jedec,lpddr2-s4"
7 "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
9 "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
11 "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
35 - The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
36 "lpddr2-timings" provides AC timing parameters of the device for
39 bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings"
43 elpida_ECB240ABACN : lpddr2 {
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H A Dlpddr2-timings.txt1 * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
4 - compatible : Should be "jedec,lpddr2-timings"
33 timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
34 compatible = "jedec,lpddr2-timings";
H A Dlpddr3-timings.txt3 The structures are based on LPDDR2 and extended where needed.
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr2.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
23 - jedec,lpddr2-nvm
24 - jedec,lpddr2-s2
25 - jedec,lpddr2-s4
27 - pattern: "^lpddr2-[0-9a-f]{2},[0-9a-f]{4}$"
29 - jedec,lpddr2-nvm
30 - jedec,lpddr2-s2
31 - jedec,lpddr2-s4
128 "^lpddr2-timings":
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H A Dlpddr2-timings.txt1 * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
4 - compatible : Should be "jedec,lpddr2-timings"
33 timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
34 compatible = "jedec,lpddr2-timings";
H A Djedec,lpddr2-timings.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
14 const: jedec,lpddr2-timings
117 compatible = "jedec,lpddr2-timings";
H A Djedec,lpddr-channel.yaml21 - jedec,lpddr2-channel
67 const: jedec,lpddr2-channel
71 $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
H A Dlpddr3-timings.txt3 The structures are based on LPDDR2 and extended where needed.
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Delpida_ecb240abacn.dtsi7 elpida_ECB240ABACN: lpddr2 {
8 compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4";
24 timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
25 compatible = "jedec,lpddr2-timings";
46 timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
47 compatible = "jedec,lpddr2-timings";
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra20-emc.yaml19 standard protocols: DDR1, LPDDR2 and DDR2.
167 lpddr2:
168 $ref: ddr/jedec,lpddr2.yaml#
180 - lpddr2
242 lpddr2 {
243 compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
H A Dnvidia,tegra30-mc.yaml34 and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
H A Dnvidia,tegra30-emc.yaml18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ti/
H A Demif.txt5 DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
24 - device-handle : phandle to a "lpddr2" node representing the memory part
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-asus-tf201.dts113 /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */
168 /* TF201 Unknown 1GB LPDDR2 500MHZ */
225 /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */
405 /* TF201 Unknown 1GB LPDDR2 500MHZ */
H A Dtegra30-lg-p895.dts117 /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */
194 /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */
H A Dtegra20-asus-tf101.dts861 lpddr2 {
862 compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";