| /linux/arch/powerpc/kernel/ |
| H A D | cpu_setup_power.c | 29 static void init_LPCR_ISA300(u64 lpcr, u64 lpes) in init_LPCR_ISA300() argument
32 lpcr |= (lpes << LPCR_LPES_SH) & LPCR_LPES; in init_LPCR_ISA300()
33 lpcr |= LPCR_PECE0|LPCR_PECE1|LPCR_PECE2; in init_LPCR_ISA300()
34 lpcr |= (4ull << LPCR_DPFD_SH) & LPCR_DPFD; in init_LPCR_ISA300()
35 lpcr &= ~LPCR_HDICE; /* clear HDICE */ in init_LPCR_ISA300()
36 lpcr |= (4ull << LPCR_VC_SH); in init_LPCR_ISA300()
37 mtspr(SPRN_LPCR, lpcr); in init_LPCR_ISA300()
42 * Setup a sane LPCR:
43 * Called with initial LPCR and desired LPES 2-bit value
54 static void init_LPCR_ISA206(u64 lpcr, u64 lpes) in init_LPCR_ISA206() argument
[all …]
|
| H A D | exceptions-64s.S | 202 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be
803 * Interrupt Location (AIL) bit set in the LPCR. However this does not
1609 * When running in HV mode, Linux sets up the LPCR[LPES] bit such that
1613 * On bare metal POWER9 and later, Linux sets the LPCR[HVICE] bit such that
|
| /linux/arch/powerpc/kvm/ |
| H A D | book3s_hv_builtin.c | 539 * Perform MSR and PC adjustment for LPCR[AIL]=3 if it is set and in inject_interrupt()
547 (vcpu->arch.vcore->lpcr & LPCR_AIL) == LPCR_AIL_3 && in inject_interrupt()
573 unsigned long lpcr; in kvmppc_guest_entry_inject_int() local
577 /* Insert EXTERNAL bit into LPCR at the MER bit position */ in kvmppc_guest_entry_inject_int()
579 lpcr = mfspr(SPRN_LPCR); in kvmppc_guest_entry_inject_int()
580 lpcr |= ext << LPCR_MER_SH; in kvmppc_guest_entry_inject_int()
581 mtspr(SPRN_LPCR, lpcr); in kvmppc_guest_entry_inject_int()
589 if (!(lpcr & LPCR_LD)) in kvmppc_guest_entry_inject_int()
|
| H A D | book3s_hv_p9_entry.c | 301 static void switch_mmu_to_guest_radix(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr) in switch_mmu_to_guest_radix() argument
318 mtspr(SPRN_LPCR, lpcr); in switch_mmu_to_guest_radix()
326 static void switch_mmu_to_guest_hpt(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr) in switch_mmu_to_guest_hpt() argument
343 mtspr(SPRN_LPCR, lpcr); in switch_mmu_to_guest_hpt()
356 u64 lpcr = kvm->arch.host_lpcr; in switch_mmu_to_host() local
368 mtspr(SPRN_LPCR, lpcr); in switch_mmu_to_host()
532 int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr, u64 *tb) in kvmhv_vcpu_entry_p9() argument
698 switch_mmu_to_guest_radix(kvm, vcpu, lpcr); in kvmhv_vcpu_entry_p9()
700 switch_mmu_to_guest_hpt(kvm, vcpu, lpcr); in kvmhv_vcpu_entry_p9()
706 * P9 suppresses the HDEC exception when LPCR[HDICE] = 0, in kvmhv_vcpu_entry_p9()
[all …]
|
| H A D | book3s_hv_interrupts.S | 63 * we need to set LPCR[HDICE] before writing HDEC.
|
| H A D | book3s_hv_rmhandlers.S | 110 * we reloaded the host's LPCR value.
162 /* Set LPCR. */
817 /* Set LPCR. */
2173 * occurs, with PECE1 and PECE0 set in LPCR.
2190 kvm_nap_sequence: /* desired LPCR value in r5 */
|
| /linux/drivers/gpu/drm/imx/lcdc/ |
| H A D | imx-lcdc.c | 71 /* Values for LPCR Register */
145 u32 lpcr, lvcr, lhcr; in imx_lcdc_update_hw_registers() local
177 lpcr = readl(lcdc->base + IMX21LCDC_LPCR); in imx_lcdc_update_hw_registers()
178 lpcr &= ~IMX21LCDC_LPCR_BPIX; in imx_lcdc_update_hw_registers()
179 lpcr |= FIELD_PREP(IMX21LCDC_LPCR_BPIX, imx_lcdc_get_format(fb->format->format)); in imx_lcdc_update_hw_registers()
180 writel(lpcr, lcdc->base + IMX21LCDC_LPCR); in imx_lcdc_update_hw_registers()
|
| /linux/drivers/rtc/ |
| H A D | rtc-snvs.c | 137 u32 lpcr; in snvs_rtc_enable() local
143 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr); in snvs_rtc_enable()
146 if (lpcr & SNVS_LPCR_SRTC_ENV) in snvs_rtc_enable()
149 if (!(lpcr & SNVS_LPCR_SRTC_ENV)) in snvs_rtc_enable()
|
| /linux/arch/powerpc/include/asm/ |
| H A D | pnv-ocxl.h | 79 uint64_t lpcr, void __iomem **arva);
|
| H A D | opal.h | 32 uint64_t lpcr);
|
| /linux/Documentation/devicetree/bindings/crypto/ |
| H A D | fsl,sec-v4.0-mon.yaml | 125 SNVS_LP LPCR register.
|
| /linux/arch/powerpc/platforms/powernv/ |
| H A D | ocxl.c | 487 uint64_t lpcr, void __iomem **arva) in pnv_ocxl_map_lpar() argument
509 lparid, lpcr); in pnv_ocxl_map_lpar()
|
| H A D | vas-window.c | 276 u64 lpcr, val; in init_xlate_regs() local
291 lpcr = mfspr(SPRN_LPCR); in init_xlate_regs()
301 val = SET_FIELD(VAS_XLATE_LPCR_ISL, val, lpcr & LPCR_ISL); in init_xlate_regs()
302 val = SET_FIELD(VAS_XLATE_LPCR_TC, val, lpcr & LPCR_TC); in init_xlate_regs()
|
| /linux/tools/testing/selftests/powerpc/nx-gzip/include/ |
| H A D | nxu.h | 167 * translation information, such as MSR and LPCR bits, job
|
| /linux/Documentation/arch/powerpc/ |
| H A D | kvm-nested.rst | 481 | 0x102C | 0x08 | RW | T | LPCR |
|