Searched +full:lpc +full:- +full:to +full:- +full:ahb (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/mfd/aspeed-lp[all...]
2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth7 primary use case of the Aspeed LPC controller is as a slave on the bus11 The LPC controller is represented as a multi-function device to account for the12 mix of functionality, which includes, but is not limited to:16 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the17 physical properties of some LPC pins, configuration of serial IRQs, and18 APB-to-LPC bridging amonst other functions.20 * An LPC Host Interface Controller: Manages functions exposed to the host such21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>9 #include <dt-bindings/clock/lpc32xx-clock.h>10 #include <dt-bindings/interrupt-controller/irq.h>13 #address-cells = <1>;14 #size-cells = <1>;16 interrupt-parent = <&mic>;19 #address-cells = <1>;20 #size-cells = <0>;23 compatible = "arm,arm926ej-s";[all …]