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/linux/drivers/pci/pcie/
H A Daspm.c73 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); in pci_configure_aspm_l1ss()
78 pci_err(pdev, "unable to allocate ASPM L1SS save buffer (%pe)\n", in pci_configure_aspm_l1ss()
89 * If this is a Downstream Port, we never restore the L1SS state in pci_save_aspm_l1ss_state()
96 if (!pdev->l1ss || !parent->l1ss) in pci_save_aspm_l1ss_state()
108 pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cap++); in pci_save_aspm_l1ss_state()
109 pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cap++); in pci_save_aspm_l1ss_state()
120 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, cap++); in pci_save_aspm_l1ss_state()
121 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, cap++); in pci_save_aspm_l1ss_state()
140 if (!pdev->l1ss || !parent->l1ss) in pci_restore_aspm_l1ss_state()
155 /* Make sure L0s/L1 are disabled before updating L1SS config */ in pci_restore_aspm_l1ss_state()
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/linux/Documentation/devicetree/bindings/pci/
H A Dbrcm,stb-pcie.yaml74 not provide any power savings; "no-l1ss" -- which provides Clock
75 Power Management, L0s, and L1, but cannot provide L1 substate (L1SS)
76 power savings. If the downstream device connected to the RC is L1SS
77 capable AND the OS enables L1SS, all PCIe traffic may abruptly halt,
79 and L1SS, but not compliant to provide Clock Power Management;
85 enum: [ safe, no-l1ss, default ]
/linux/drivers/pci/controller/
H A Dpcie-brcmstb.c855 * Set L1SS sub-state timers to avoid lengthy state transitions, in brcm_pcie_post_setup_bcm2712()
1240 * access timeout may occur during L1SS sleep periods, even without the
1247 u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ in brcm_extend_rbus_timeout()
1274 if (strcmp(mode, "no-l1ss") == 0) { in brcm_config_clkreq()
1276 * "no-l1ss" -- Provides Clock Power Management, L0s, and in brcm_config_clkreq()
1277 * L1, but cannot provide L1 substate (L1SS) power in brcm_config_clkreq()
1279 * L1SS capable AND the OS enables L1SS, all PCIe traffic in brcm_config_clkreq()
1287 * "no-l1ss" mode. in brcm_config_clkreq()
1295 * "default" -- Provides L0s, L1, and L1SS, but not in brcm_config_clkreq()
/linux/arch/x86/pci/
H A Dfixup.c891 /* Fixup the header of L1SS Capability if missing */ in chromeos_fixup_apl_pci_l1ss_capability()
895 pci_info(dev, "restore L1SS Capability header (was %#010x now %#010x)\n", in chromeos_fixup_apl_pci_l1ss_capability()
899 /* Fixup the link to L1SS Capability if missing */ in chromeos_fixup_apl_pci_l1ss_capability()
/linux/drivers/misc/cardreader/
H A Drtsx_pcr.c1318 int err, l1ss; in rtsx_pci_init_chip() local
1408 l1ss = pci_find_ext_capability(pcr->pci, PCI_EXT_CAP_ID_L1SS); in rtsx_pci_init_chip()
1409 if (l1ss) { in rtsx_pci_init_chip()
1410 pci_read_config_dword(pcr->pci, l1ss + PCI_L1SS_CTL1, &lval); in rtsx_pci_init_chip()
/linux/drivers/pci/controller/dwc/
H A Dpcie-qcom-ep.c469 /* Request to exit from L1SS for MSI and LTR MSG */ in qcom_pcie_perst_deassert()
527 /* Gate Master AXI clock to MHI bus during L1SS */ in qcom_pcie_perst_deassert()
H A Dpcie-tegra194.c477 /* If EP doesn't advertise L1SS, just return */ in tegra_pcie_ep_irq_thread()
934 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in tegra_pcie_dw_host_init()
1860 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in pex_ep_event_pex_rst_deassert()
H A Dpcie-designware-host.c1032 * If L1SS is supported, then do not put the link into L2 as some in dw_pcie_suspend_noirq()
H A Dpcie-qcom.c987 /* Enable L1 and L1SS */ in qcom_pcie_init_2_7_0()
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c871 /* gate_tx_pck_sel length select work for L1SS */ in rk3576_combphy_cfg()
/linux/include/linux/
H A Dpci.h406 u16 l1ss; /* L1SS Capability pointer */ member
/linux/drivers/net/wireless/ath/ath10k/
H A Dwmi.h3918 /* L1SS state machine enable */
4017 /* L1SS state machine enable */