| /linux/Documentation/fb/ |
| H A D | viafb.modes | 14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
81 # Scan Frequency 50.900 kHz 100.00 Hz
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
102 # Scan Frequency 61.800 kHz 120.00 Hz
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| /linux/sound/ppc/ |
| H A D | awacs.h | 112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
116 #define SAMPLERATE_16000 (0x4 << 3) /* 16 or 14.7 kHz */
117 #define SAMPLERATE_12000 (0x5 << 3) /* 12 or 11.025 kHz */
118 #define SAMPLERATE_9600 (0x6 << 3) /* 9.6 or 8.82 kHz */
119 #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */
172 #define RATE_48000 (0x0 << 8) /* 48 kHz */
173 #define RATE_44100 (0x0 << 8) /* 44.1 kHz */
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | ti,j721e-cpb-audio.yaml | 18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
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| H A D | ti,j721e-cpb-ivi-audio.yaml | 23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
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| /linux/drivers/gpu/drm/amd/display/include/ |
| H A D | grph_object_ctrl_defs.h | 128 uint32_t pixel_clk; /* in KHz */
164 uint32_t crystal_frequency; /* in KHz */
165 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
166 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
167 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
168 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
176 uint32_t max_pixel_clock; /* in KHz */
177 uint32_t default_display_engine_pll_frequency; /* in KHz */
178 uint32_t external_clock_source_frequency_for_dp; /* in KHz */
179 uint32_t smu_gpu_pll_output_freq; /* in KHz */
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| /linux/drivers/video/fbdev/core/ |
| H A D | modedb.c | 39 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
43 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
47 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
51 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
55 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
59 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
63 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
67 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
72 /* 640x480 @ 85 Hz, 43.27 kHz hsync */
76 /* 1152x864 @ 89 Hz interlaced, 44 kHz hsync */
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| /linux/tools/testing/selftests/alsa/ |
| H A D | pcm-test.conf | 2 description "8kHz mono large periods"
11 description "8kHz stereo large periods"
20 description "44.1kHz stereo large periods"
29 description "48kHz stereo small periods"
38 description "48kHz stereo large periods"
47 description "48kHz 6 channel large periods"
56 description "96kHz stereo large periods"
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | nv40.c | 47 u32 ref = 27000, khz = 0; in read_pll_1() local
50 khz = ref * N / M; in read_pll_1()
52 return khz >> P; in read_pll_1()
66 u32 ref = 27000, khz = 0; in read_pll_2() local
69 khz = ref * N1 / M1; in read_pll_2()
72 khz = khz * N2 / M2; in read_pll_2()
74 khz = 0; in read_pll_2()
78 return khz >> P; in read_pll_2()
124 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, in nv40_clk_calc_pll() argument
135 if (khz < pll.vco1.max_freq) in nv40_clk_calc_pll()
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| H A D | gt215.c | 187 gt215_clk_info(struct nvkm_clk *base, int idx, u32 khz, in gt215_clk_info() argument
196 switch (khz) { in gt215_clk_info()
199 return khz; in gt215_clk_info()
202 return khz; in gt215_clk_info()
205 return khz; in gt215_clk_info()
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
210 diff = ((khz + 3000) - oclk); in gt215_clk_info()
235 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz, in gt215_pll_info() argument
248 ret = gt215_clk_info(&clk->base, idx, khz, info); in gt215_pll_info()
249 diff = khz - ret; in gt215_pll_info()
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| /linux/Documentation/sound/cards/ |
| H A D | audiophile-usb.rst | 48 * sample rate from 8kHz to 96kHz
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
66 * 24-bit/96kHz ==> 2 channels in _or_ 2 channels out (half duplex only)
197 - 16bits 48kHz mode with Di disabled
204 - 16bits 48kHz mode with Di enabled
234 - 24bits 48kHz mode with Di disabled
241 - 24bits 48kHz mode with Di enabled
249 - 24bits 96kHz mode
266 - 16bits 48kHz mode with only the Do port enabled
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| /linux/sound/firewire/dice/ |
| H A D | dice-weiss.c | 13 // Weiss DAC202: 192kHz 2-channel DAC
19 // Weiss MAN301: 192kHz 2-channel music archive network player
25 // Weiss INT202: 192kHz unidirectional 2-channel digital Firewire nterface
31 // Weiss INT203: 192kHz bidirectional 2-channel digital Firewire nterface
37 // Weiss ADC2: 192kHz A/D converter with microphone preamps and line nputs
43 // Weiss DAC2/Minerva: 192kHz 2-channel DAC
49 // Weiss Vesta: 192kHz 2-channel Firewire to AES/EBU interface
55 // Weiss AFI1: 192kHz 24-channel Firewire to ADAT or AES/EBU interface
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| /linux/drivers/media/dvb-frontends/ |
| H A D | tda8261.h | 12 TDA8261_STEP_2000 = 0, /* 2000 kHz */
13 TDA8261_STEP_1000, /* 1000 kHz */
14 TDA8261_STEP_500, /* 500 kHz */
15 TDA8261_STEP_250, /* 250 kHz */
16 TDA8261_STEP_125 /* 125 kHz */
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| H A D | mxl5xx_defs.h | 396 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
397 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
398 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
399 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
404 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
700 MXL_HYDRA_DISEQC_CARRIER_FREQ_22KHZ = 0, /* DiSEqC signal frequency of 22 KHz */
701 MXL_HYDRA_DISEQC_CARRIER_FREQ_33KHZ, /* DiSEqC signal frequency of 33 KHz */
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| /linux/Documentation/i2c/busses/ |
| H A D | i2c-ismt.rst | 21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
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| /linux/include/sound/ |
| H A D | designware_i2s.h | 16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
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| /linux/sound/pci/ca0106/ |
| H A D | ca0106.h | 144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
232 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
233 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
234 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
407 /* Estimated sample rate [19:0] Relative to 48kHz. 0x8000 = 1.0
416 * Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
417 * Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
419 * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
421 * I2S input rate master mode [15:14] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 445 ULONG ulClockFreq:24; // in unit of 10kHz
447 ULONG ulClockFreq:24; // in unit of 10kHz
584 ULONG ulTargetEngineClock; //In 10Khz unit
589 ULONG ulTargetEngineClock; //In 10Khz unit
598 ULONG ulTargetMemoryClock; //In 10Khz unit
603 ULONG ulTargetMemoryClock; //In 10Khz unit
612 ULONG ulDefaultEngineClock; //In 10Khz unit
613 ULONG ulDefaultMemoryClock; //In 10Khz unit
676 USHORT usPixelClock; // in 10KHz; for bios convenient
692 USHORT usPixelClock; // in 10KHz; for bios convenient
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| /linux/arch/arm/mach-omap1/ |
| H A D | timer32k.c | 59 * 32KHz OS timer
62 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
63 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
65 * with the 32KHz synchronized timer.
152 IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL)) in omap_init_32k_timer()
153 pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER); in omap_init_32k_timer()
167 * 32KHz clocksource ... always available, on pretty most chips except
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 479 ULONG ulClockFreq:24; // in unit of 10kHz
481 ULONG ulClockFreq:24; // in unit of 10kHz
687 ULONG ulTargetEngineClock; //In 10Khz unit
692 ULONG ulTargetEngineClock; //In 10Khz unit
698 ULONG ulTargetEngineClock; //In 10Khz unit
708 ULONG ulTargetMemoryClock; //In 10Khz unit
713 ULONG ulTargetMemoryClock; //In 10Khz unit
722 ULONG ulDefaultEngineClock; //In 10Khz unit
723 ULONG ulDefaultMemoryClock; //In 10Khz unit
740 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit
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| /linux/drivers/media/tuners/ |
| H A D | tda9887.c | 276 "- 12.5 kHz", in dump_read_message()
277 "- 37.5 kHz", in dump_read_message()
278 "- 62.5 kHz", in dump_read_message()
279 "- 87.5 kHz", in dump_read_message()
280 "-112.5 kHz", in dump_read_message()
281 "-137.5 kHz", in dump_read_message()
282 "-162.5 kHz", in dump_read_message()
283 "-187.5 kHz [min]", in dump_read_message()
284 "+187.5 kHz [max]", in dump_read_message()
285 "+162.5 kHz", in dump_read_message()
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| /linux/Documentation/arch/arm/sunxi/ |
| H A D | clocks.rst | 18 24MHz 32kHz
26 When you are about to suspend, you switch the CPU Mux to the 32kHz
29 24Mhz 32kHz
39 32kHz
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| /linux/drivers/cpufreq/ |
| H A D | cpufreq_userspace.c | 27 * @freq: target frequency in kHz
36 pr_debug("cpufreq_set for cpu %u, freq %u kHz\n", policy->cpu, freq); in cpufreq_set()
113 pr_debug("limit event for cpu %u: %u - %u kHz, currently %u kHz, last set to %u kHz\n", in cpufreq_userspace_policy_limits()
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| H A D | gx-suspmod.c | 132 * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
217 static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, in gx_validate_speed() argument
229 tmp_off = ((khz * i) / stock_freq) & 0xff; in gx_validate_speed()
232 /* if this relation is closer to khz, use this. If it's equal, in gx_validate_speed()
234 if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) { in gx_validate_speed()
247 * set cpu speed in khz.
250 static void gx_set_cpuspeed(struct cpufreq_policy *policy, unsigned int khz) in gx_set_cpuspeed() argument
259 new_khz = gx_validate_speed(khz, &gx_params->on_duration, in gx_set_cpuspeed()
268 /* if new khz == 100% of CPU speed, it is special case */ in gx_set_cpuspeed()
317 pr_debug("suspend modulation w/ clock speed: %d kHz.\n", freqs.new); in gx_set_cpuspeed()
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| /linux/Documentation/hwmon/ |
| H A D | lm85.rst | 153 driven by a 22.5 kHz clock. This is a global mode, not per-PWM output,
154 which means that setting any PWM frequency above 11.3 kHz will switch
155 all 3 PWM outputs to a 22.5 kHz frequency. Conversely, setting any PWM
156 frequency below 11.3 kHz will switch all 3 PWM outputs to a frequency
179 The LM96000 supports additional high frequency PWM modes (22.5 kHz, 24 kHz,
180 25.7 kHz, 27.7 kHz and 30 kHz), which can be configured on a per-PWM basis.
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| /linux/drivers/net/wireless/st/cw1200/ |
| H A D | main.c | 487 /* Clock is in KHz */
491 case 0x32C8: /* 13000 KHz */ in cw1200_dpll_from_clk()
493 case 0x3E80: /* 16000 KHz */ in cw1200_dpll_from_clk()
495 case 0x41A0: /* 16800 KHz */ in cw1200_dpll_from_clk()
497 case 0x4B00: /* 19200 KHz */ in cw1200_dpll_from_clk()
499 case 0x5DC0: /* 24000 KHz */ in cw1200_dpll_from_clk()
501 case 0x6590: /* 26000 KHz */ in cw1200_dpll_from_clk()
503 case 0x8340: /* 33600 KHz */ in cw1200_dpll_from_clk()
505 case 0x9600: /* 38400 KHz */ in cw1200_dpll_from_clk()
507 case 0x9C40: /* 40000 KHz */ in cw1200_dpll_from_clk()
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