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/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dinterconnect.txt1 Interconnect Provider Device Tree Bindings
4 The purpose of this document is to define a common set of generic interconnect
8 = interconnect providers =
10 The interconnect provider binding is intended to represent the interconnect
11 controllers in the system. Each provider registers a set of interconnect
12 nodes, which expose the interconnect related capabilities of the interconnect
14 etc. The consumer drivers set constraints on interconnect path (or endpoints)
15 depending on the use case. Interconnect providers can also be interconnect
20 - compatible : contains the interconnect provider compatible string
21 - #interconnect-cells : number of cells in a interconnect specifier needed to
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H A Dqcom,qcm2290.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,qcm2290.yaml#
7 title: Qualcomm QCM2290 Network-On-Chip interconnect
13 The Qualcomm QCM2290 interconnect providers support adjusting the
31 '^interconnect-[a-z0-9]+$':
34 The interconnect providers do not have a separate QoS register space,
62 snoc: interconnect@1880000 {
65 #interconnect-cells = <1>;
67 qup_virt: interconnect-qup {
69 #interconnect-cells = <1>;
72 mmnrt_virt: interconnect
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H A Dqcom,sdm660.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml#
7 title: Qualcomm SDM660 Network-On-Chip interconnect
13 The Qualcomm SDM660 interconnect providers support adjusting the
88 bimc: interconnect@1008000 {
91 #interconnect-cells = <1>;
94 a2noc: interconnect@1704000 {
97 #interconnect-cells = <1>;
H A Dqcom,sm6350-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm6350-rpmh.yaml#
7 title: Qualcomm SM6350 RPMh Network-On-Chip Interconnect
13 Qualcomm RPMh-based interconnect provider on SM6350.
33 '#interconnect-cells': true
36 '^interconnect-[a-z0-9\-]+$':
39 The interconnect providers do not have a separate QoS register space,
49 '#interconnect-cells': true
64 config_noc: interconnect@1500000 {
67 #interconnect-cells = <2>;
71 system_noc: interconnect@1620000 {
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H A Dqcom,msm8953.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8953.yaml#
7 title: Qualcomm MSM8953 Network-On-Chip interconnect
13 The Qualcomm MSM8953 interconnect providers support adjusting the
16 See also: include/dt-bindings/interconnect/qcom,msm8953.h
34 '#interconnect-cells':
38 '^interconnect-[a-z0-9\-]+$':
43 The interconnect providers do not have a separate QoS register space,
52 - '#interconnect-cells'
57 - '#interconnect-cells'
89 snoc: interconnect@580000 {
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H A Dqcom,sc7180.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sc7180.yaml#
7 title: Qualcomm SC7180 Network-On-Chip Interconnect
13 SC7180 interconnect providers support system bandwidth requirements through
40 '#interconnect-cells':
47 this interconnect to send RPMh commands.
57 - '#interconnect-cells'
64 #include <dt-bindings/interconnect/qcom,sc7180.h>
66 config_noc: interconnect@1500000 {
69 #interconnect-cells = <1>;
73 system_noc: interconnect@1620000 {
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H A Dqcom,sm7150-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm7150-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM7150
13 RPMh interconnect providers support system bandwidth requirements through
16 See also:: include/dt-bindings/interconnect/qcom,sm7150-rpmh.h
39 '^interconnect-[0-9]+$':
42 The interconnect providers do not have a separate QoS register space,
66 mc_virt: interconnect@1380000 {
69 #interconnect-cells = <2>;
73 system_noc: interconnect@1620000 {
76 #interconnect-cells = <2>;
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H A Dqcom,msm8916.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8916.yaml#
7 title: Qualcomm MSM8916 Network-On-Chip interconnect
13 The Qualcomm MSM8916 interconnect providers support adjusting the
26 '#interconnect-cells':
42 - '#interconnect-cells'
52 bimc: interconnect@400000 {
55 #interconnect-cells = <1>;
61 pcnoc: interconnect@500000 {
64 #interconnect-cells = <1>;
70 snoc: interconnect@580000 {
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H A Dqcom,qcs404.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,qcs404.yaml#
7 title: Qualcomm QCS404 Network-On-Chip interconnect
13 The Qualcomm QCS404 interconnect providers support adjusting the
26 '#interconnect-cells':
42 - '#interconnect-cells'
52 bimc: interconnect@400000 {
55 #interconnect-cells = <1>;
61 pnoc: interconnect@500000 {
64 #interconnect-cells = <1>;
70 snoc: interconnect@580000 {
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H A Dqcom,sdm845.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sdm845.yaml#
7 title: Qualcomm SDM845 Network-On-Chip Interconnect
13 SDM845 interconnect providers support system bandwidth requirements through
35 '#interconnect-cells':
42 this interconnect to send RPMh commands.
52 - '#interconnect-cells'
59 #include <dt-bindings/interconnect/qcom,sdm845.h>
61 mem_noc: interconnect@1380000 {
64 #interconnect-cells = <1>;
68 mmss_noc: interconnect@1740000 {
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H A Dqcom,sc7280-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sc7280-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SC7280
14 RPMh interconnect providers support system bandwidth requirements through
17 See also:: include/dt-bindings/interconnect/qcom,sc7280.h
104 interconnect {
106 #interconnect-cells = <2>;
110 interconnect@9100000 {
113 #interconnect-cells = <2>;
117 interconnect@16e0000 {
120 #interconnect-cells = <2>;
H A Dqcom,qdu1000-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,qdu1000-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on QDU1000
14 RPMh interconnect providers support system bandwidth requirements through
29 '#interconnect-cells': true
57 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
59 system_noc: interconnect@1640000 {
62 #interconnect-cells = <2>;
66 clk_virt: interconnect-0 {
68 #interconnect-cells = <2>;
H A Dqcom,msm8939.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8939.yaml#
7 title: Qualcomm MSM8937/MSM8939/MSM8976 Network-On-Chip interconnect
13 The Qualcomm MSM8937/MSM8939/MSM8976 interconnect providers support
36 '^interconnect-[a-z0-9\-]+$':
40 The interconnect providers do not have a separate QoS register space,
68 snoc: interconnect@580000 {
71 #interconnect-cells = <1>;
73 snoc_mm: interconnect-snoc {
75 #interconnect-cells = <1>;
H A Dqcom,msm8974.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8974.yaml#
7 title: Qualcomm MSM8974 Network-On-Chip Interconnect
13 The Qualcomm MSM8974 interconnect providers support setting system
29 '#interconnect-cells':
45 - '#interconnect-cells'
55 bimc: interconnect@fc380000 {
58 #interconnect-cells = <1>;
H A Dqcom,sm8450-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450
14 RPMh interconnect providers support system bandwidth requirements through
17 See also:: include/dt-bindings/interconnect/qcom,sm8450.h
109 interconnect-0 {
111 #interconnect-cells = <2>;
115 interconnect@1700000 {
118 #interconnect-cells = <2>;
H A Dqcom,osm-l3.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests
51 '#interconnect-cells':
59 - '#interconnect-cells'
69 osm_l3: interconnect@17d41000 {
76 #interconnect-cells = <1>;
H A Dqcom,sm8550-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550
14 RPMh interconnect providers support system bandwidth requirements through
21 See also:: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h
126 clk_virt: interconnect-0 {
128 #interconnect-cells = <2>;
132 aggre1_noc: interconnect@16e0000 {
135 #interconnect-cells = <2>;
H A Dqcom,rpmh-common.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,rpmh-common.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect
14 RPMh interconnect providers support system bandwidth requirements through
22 '#interconnect-cells':
32 this interconnect to send RPMh commands.
40 - '#interconnect-cells'
H A Dqcom,sc8280xp-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sc8280xp-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SC8280XP
14 RPMh interconnect providers support system bandwidth requirements through
17 See also:: include/dt-bindings/interconnect/qcom,sc8280xp.h
45 interconnect-0 {
47 #interconnect-cells = <2>;
H A Dqcom,rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect
14 RPMh interconnect providers support system bandwidth requirements through
104 '#interconnect-cells': true
130 #include <dt-bindings/interconnect/qcom,sdm845.h>
132 mem_noc: interconnect@1380000 {
135 #interconnect-cells = <1>;
139 mmss_noc: interconnect@1740000 {
142 #interconnect-cells = <1>;
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dti-sysc.txt1 Texas Instruments sysc interconnect target module wrapper binding
3 Texas Instruments SoCs can have a generic interconnect target module
5 interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
8 of the interconnect.
10 Each interconnect target module can have one or more devices connected to
11 it. There is a set of control registers for managing interconnect target
12 module clocks, idle modes and interconnect level resets for the module.
15 space of the first child device IP block managed by the interconnect
43 - reg shall have register areas implemented for the interconnect
47 interconnect target module in question such as
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H A Dti-sysc.yaml7 title: Texas Instruments interconnect target module
13 Texas Instruments SoCs can have a generic interconnect target module
14 for devices connected to various interconnects such as L3 interconnect
15 using Arteris NoC, and L4 interconnect using Sonics s3220. This module
18 than that it is mostly independent of the interconnect.
20 Each interconnect target module can have one or more devices connected to
21 it. There is a set of control registers for managing the interconnect target
22 module clocks, idle modes and interconnect level resets.
24 The interconnect target module control registers are sprinkled into the
26 the interconnect target module. Typically the register names are REVISION,
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H A Dbaikal,bt1-axi.yaml16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
22 (Errors Handler Block) embedded on top of the DW AXI Interconnect and
36 - description: Synopsys DesignWare AXI Interconnect QoS registers
45 '#interconnect-cells':
57 - description: Main Interconnect uplink reference clock
65 - description: Main Interconnect reset line
93 #interconnect-cells = <1>;
/freebsd/sys/contrib/device-tree/Bindings/soc/imx/
H A Dfsl,imx8mm-vpu-blk-ctrl.yaml44 interconnect-names:
91 - description: G1 decoder interconnect
92 - description: G2 decoder interconnect
95 interconnect-names:
136 - description: G1 decoder interconnect
137 - description: G2 decoder interconnect
138 - description: VC8000E encoder interconnect
140 interconnect-names:
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.txt37 should have the interconnect endpoints set to the Memory Client and External
58 - interconnect-names: Must include name of the interconnect path for each
59 interconnect entry. Consult TRM documentation for information about
143 - interconnect-names: Must include name of the interconnect path for each
144 interconnect entry. Consult TRM documentation for information about
164 - interconnect-names: Must include name of the interconnect path for each
165 interconnect entry. Consult TRM documentation for information about
185 - interconnect-names: Must include name of the interconnect path for each
186 interconnect entry. Consult TRM documentation for information about
206 - interconnect-names: Must include name of the interconnect path for each
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