Searched +full:inter +full:- +full:hart (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Palmer Dabbelt <palmer@dabbelt.com>11 - Anup Patel <anup.patel@wdc.com>14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor16 interrupts. It directly connects to the timer and inter-processor interrupt17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local19 The clock frequency of CLINT is specified via "timebase-frequency" DT[all …]
2 * refclock_arc - clock driver for ARCRON MSF/DCF/WWVB receivers35 Modifications by Damon Hart-Davis, <d@hd.org>, 1997.37 Modifications by Christopher Price, <cprice@cs-home.com>, 2003.44 Orginally developed and used with ntp3-5.85 by Derek Mulcahy.46 Built against ntp3-5.90 on Solaris 2.5 using gcc 2.7.2.52 ----[all...]
12 A-b-c book13 A-b-c method14 abdomino-uterotomy15 Abdul-baha16 a-be20 able-bodied21 able-bodiedness22 able-minded23 able-mindedness27 Abor-miri[all …]
82654 hart95882 inter99810 Jean-Christophe99811 Jean-Pierre
2 %%% BibTeX-file{23 %%% (incompletely) 1970 -- 1979.50 %%% covering 1958--1996 became too large (about65 %%% Algorithms 1--492. For Algorithms 493--686,72 %%% cross-referenced in both directions, so75 %%% Corrigenda. Cross-referenced entries are77 %%% that each is completely self-contained.83 %%% ftp://netlib.bell-labs.com/netlib/toms.88 %%% http://ciir.cs.umass.edu/cgi-bin/web_query_form/public/cacm2.1.90 %%% The initial draft of entries for 1981 --[all …]