| /freebsd/sys/contrib/device-tree/Bindings/powerpc/nintendo/ |
| H A D | wii.txt | 11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupt
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <broonie@kernel.org>
27 - minimum: 0
30 Chip select used by the device.
[all …]
|
| /freebsd/contrib/ntp/html/ |
| H A D | clock.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
12 <!-- #BeginDate format:En2m -->4-Aug-2011 23:40<!-- #EndDate -->
20 <li class="inline"><a href="#inter">Operating Intervals</a></li>
28 …-of-year (TOY) chip to maintain the time when the power is off. When the computer is restarted, t…
31 …emon sets the step threshold to 600 s using the <tt>-x</tt> option on the command line. If the <tt…
33 …idered before using these options. The slew rate is fixed at 500 parts-per-million (PPM) by th…
35 <p>When the daemon is started after a considerable downtime, it could be the TOY chip clock has dri…
36 <h4 id="inter">Operating Intervals</h4>
51 <dt>FSET - The frequency file is present</dt>
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/i2c/ |
| H A D | i2c-mxs.txt | 1 * Freescale MXS Inter IC (I2C) Controller
4 - compatible: Should be "fsl,<chip>-i2c"
5 - reg: Should contain registers location and length
6 - interrupts: Should contain ERROR interrupt number
7 - clock-frequency: Desired I2C bus clock frequency in Hz.
9 - dmas: DMA specifier, consisting of a phandle to DMA controller node
11 Refer to dma.txt and fsl-mxs-dma.txt for details.
12 - dma-names: Must be "rx-tx".
17 #address-cells = <1>;
18 #size-cells = <0>;
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | iicbus.4 | 41 system provides a uniform, modular and architecture-independent
45 I2C is an acronym for Inter Integrated Circuit bus.
49 easy way to connect a CPU to peripheral chips in a TV-set.
57 is a CPU, LCD driver, memory, or complex function chip.
60 Obviously an LCD driver is only a receiver, while a memory or I/O chip can
65 The BUS MASTER is the chip issuing the commands on the BUS.
71 As mentioned before, the IC bus is a Multi-MASTER BUS.
77 .Bl -column "Device drivers" -compact
89 8-bit characters they write to the bus according to the I2C protocol.
92 bidirectional communications, thanks to the multi-master capabilities of the
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | usb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
38 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
40 serial is specified and High-Speed Inter-Chip feature if HSIC is
46 maximum-speed:
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | mediatek,mdp3-rdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
24 - enum:
25 - mediatek,mt8183-mdp3-rdma
26 - mediatek,mt8188-mdp3-rdma
27 - mediatek,mt8195-mdp3-rdma
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | st,stih4xx.txt | 3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
[all …]
|
| /freebsd/sys/dev/le/ |
| H A D | lancereg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
[all …]
|
| /illumos-gate/usr/src/man/man4d/ |
| H A D | hme.4d | 8 hme \- SUNW,hme Fast-Ethernet device driver
18 The \fBSUNW,hme\fR Fast-Ethernet driver is a multi-threaded, loadable,
20 Provider Interface, \fBdlpi\fR(4P), over a \fBSUNW,hme\fR Fast-Ethernet
21 controller. The motherboard and add-in SBus \fBSUNW,hme\fR controllers of
27 is used to handle the \fBSUNW,hme\fR device. Functions include chip
30 provides 100Base-TX networking interfaces using SUN's \fBFEPS ASIC\fR and an
33 Transceiver which connects to a \fBRJ-45\fR connector. In addition to the RJ-45
37 may use any physical media (copper or fiber) specified in the 100Base-TX
42 The 100Base-TX standard specifies an "auto-negotiation" protocol to
44 is capable of doing "auto-negotiation" with the remote-end of the link (Link
[all …]
|
| /illumos-gate/usr/src/uts/common/io/dmfe/ |
| H A D | dmfe_impl.h | 59 * Describes the identity of a specific chip
82 * Describes one chunk of allocated DMA-able memory
99 * Indexes into the driver-specific kstats, divided into:
119 * Actual state of the DM9102A chip
122 CHIP_ERROR = -1, /* error, need reset */
145 IOC_INVAL = -1, /* bad, NAK with EINVAL */
154 * Per-instance soft-state structure
167 uint32_t debug; /* per-instance debug */
186 * exclusive access during the bit-twiddling needed to send
188 * --S--L--O--W-- so we keep this lock separate, so that
[all …]
|
| /freebsd/sys/dev/ic/ |
| H A D | i82586.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
38 * Intel 82586 Ethernet chip
42 * chip written by Russ Nelson and others.
55 u_char ie_bus_use; /* true if 8-bit only */
57 caddr_t ie_iscp_ptr; /* 24-bit physaddr of ISCP */
68 * FIXME: some of these should be re-commented after we figure out their
74 u_short ie_scb_offset; /* 16-bit physaddr of next struct */
75 caddr_t ie_base; /* 24-bit physaddr for all 16-bit vars */
84 u_short ie_command_list; /* 16-pointer to command block list */
[all …]
|
| /freebsd/sys/dev/usb/serial/ |
| H A D | umcs.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
50 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong
52 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong
67 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */
78 /* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */
93 #define MCS7840_DEV_REG_SP1_ICG 0x2c /* Inter character gap
96 #define MCS7840_DEV_REG_SP2_ICG 0x2d /* Inter character gap
99 #define MCS7840_DEV_REG_SP3_ICG 0x2e /* Inter character gap
102 #define MCS7840_DEV_REG_SP4_ICG 0x2f /* Inter character gap
[all …]
|
| /freebsd/sys/contrib/dev/rtw88/ |
| H A D | pci.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
55 return skb->priority; in rtw_pci_get_tx_qsel()
61 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read8()
64 return readb(rtwpci->mmap + addr); in rtw_pci_read8()
68 val = bus_read_1((struct resource *)rtwpci->mmap, addr); in rtw_pci_read8()
69 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "R08 (%#010x) -> %#04x\n", addr, val); in rtw_pci_read8()
76 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read16()
79 return readw(rtwpci->mmap + addr); in rtw_pci_read16()
83 val = bus_read_2((struct resource *)rtwpci->mmap, addr); in rtw_pci_read16()
[all …]
|
| /freebsd/sys/dev/ae/ |
| H A D | if_aereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
37 #define AE_MASTER_REVNUM_SHIFT 16 /* Chip revision number. */
84 #define AE_EADDR0_REG 0x1488 /* 5 - 2 bytes */
85 #define AE_EADDR1_REG 0x148c /* 1 - 0 bytes */
89 * L2 supports 64-bit addressing but all rings base addresses
97 Should be 120-byte aligned (i.e.
99 have 128-byte alignment). */
100 #define AE_TXD_BUFSIZE_REG 0x1548 /* Size of TxD ring in 4-byte units.
101 Should be 4-byte aligned. */
[all …]
|
| /illumos-gate/usr/src/uts/common/io/rge/ |
| H A D | rge.h | 91 * RGE-specific ioctls ...
109 #define RGE_DIAG (RGE_IOC|10) /* currently a no-op */
149 * Driver chip operation parameters
173 * read-only parameters describing the hardware's capabilities
174 * read-write parameters controlling the advertised capabilities
175 * read-only parameters describing the partner's capabilities
176 * read-only parameters describing the link state
211 RGE_CHIP_FAULT = -2, /* fault, need reset */
238 IOC_INVAL = -1, /* bad, NAK with EINVAL */
259 * various address spaces (PCI config space, PCI memory-mapped I/O
[all …]
|
| /illumos-gate/usr/src/uts/sun4u/lw2plus/io/ |
| H A D | lombus.c | 28 * packet-based protocol over a serial link connected to one of the serial
29 * ports of the SuperIO (SIO) chip.
32 * registers signify - only the clients need this information.
69 #define HANDLE_ADDR(hdlp) (hdlp->ah_addr)
70 #define HANDLE_FAULT(hdlp) (hdlp->ah_fault)
71 #define HANDLE_MAPLEN(hdlp) (hdlp->ah_len)
72 #define HANDLE_PRIVATE(hdlp) (hdlp->ah_bus_private)
80 #define HANDLE_ADDR(hdlp) (hdlp->ahi_common.ah_addr)
81 #define HANDLE_FAULT(hdlp) (hdlp->ahi_fault)
82 #define HANDLE_MAPLEN(hdlp) (hdlp->ahi_common.ah_len)
[all …]
|
| /illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/ |
| H A D | lm_dmae.h | 46 * - 'Single-block' DMA operations
47 * Single-block DMA operations are composed of a single HW
49 * destination and length. Single-block DMA operations are
52 * appropriate location in host memory. Single-block DMA
55 * - SGL DMA operations
56 * SGL DMA operations use two DMAE channels - one called a
70 * - SGL DMA operations in asynchronous mode (a.k.a post/poll)
89 …DS 5 // max number of commands in a DMAE SGL (just as a limit - can be defined other…
97 …E_E1 0x0400 // maximun size (in DW) of read/write commands (HW limit) - for (chip id<=5710)
99 // up to 0xffff actually limit is 64KB-1 so 0x2000 dwords is 32KB
[all …]
|
| /illumos-gate/usr/src/uts/common/io/bge/ |
| H A D | bge_impl.h | 23 * Copyright (c) 2010-2013, by Broadcom, Inc.
93 ((uint32_t)((uint8_t *)(&((_s *)0)->_f) - \
102 * as the typedef for ether_addr_t ;-!
120 * Compile-time feature switches ...
132 * register-set numbers to use for the config space registers
133 * and the operating registers respectively. On an OBP-based
145 * has been stripped off, the packet data will be 4-byte aligned.
182 * are derived from observations and heuristics - the values below
223 * 570X-PG102-R page 56.
259 * PCI type. PCI-Express or PCI/PCIX
[all …]
|
| /freebsd/sys/contrib/ncsw/Peripherals/FM/SP/ |
| H A D | fm_sp.c | 2 * Copyright 2008-2012 Freescale Semiconductor Inc.
57 if ((err = FmSpCheckIntContextParams(&p_FmVspEntry->intContext))!= E_OK) in CheckParamsGeneratedInternally()
59 if ((err = FmSpCheckBufMargins(&p_FmVspEntry->bufMargins)) != E_OK) in CheckParamsGeneratedInternally()
70 SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE); in CheckParams()
71 SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->h_Fm, E_INVALID_HANDLE); in CheckParams()
73 if ((err = FmSpCheckBufPoolsParams(&p_FmVspEntry->p_FmVspEntryDriverParams->extBufPools, in CheckParams()
74 p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools, in CheckParams()
75 … p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion)) != E_OK) in CheckParams()
79 if (p_FmVspEntry->p_FmVspEntryDriverParams->liodnOffset & ~FM_LIODN_OFFSET_MASK) in CheckParams()
82 err = FmVSPCheckRelativeProfile(p_FmVspEntry->h_Fm, in CheckParams()
[all …]
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| /illumos-gate/usr/src/uts/common/sys/usb/hcd/openhci/ |
| H A D | ohcid.h | 126 uint16_t ohci_vendor_id; /* chip vendor */
127 uint16_t ohci_device_id; /* chip device */
128 uint8_t ohci_rev_id; /* chip revison */
134 uint_t ohci_frame_interval; /* Frme inter reg */
294 #define OHCI_INTRS_STATS(ohci) ((ohci)->ohci_intrs_stats)
296 ((ohci_intrs_stats_t *)OHCI_INTRS_STATS((ohci))->ks_data)
298 #define OHCI_TOTAL_STATS(ohci) ((ohci)->ohci_total_stats)
299 #define OHCI_TOTAL_STATS_DATA(ohci) (KSTAT_IO_PTR((ohci)->ohci_total_stats))
301 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_CONTROL]))
303 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_BULK]))
[all …]
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| /illumos-gate/usr/src/uts/common/io/yge/ |
| H A D | yge.h | 12 * are provided to you under the BSD-type license terms provided
17 * - Redistributions of source code must retain the above copyright
19 * - Redistributions in binary form must reproduce the above
23 * - Neither the name of Marvell nor the names of its contributors
57 * D-Link PCI vendor ID
91 * D-Link gigabit ethernet device ID
133 #define PCI_Y2_PIG_ENA BIT(31) /* Enable Plug-in-Go (YUKON-2) */
134 #define PCI_Y2_DLL_DIS BIT(30) /* Disable PCI DLL (YUKON-2) */
135 #define PCI_Y2_PHY2_COMA BIT(29) /* Set PHY 2 to Coma Mode (YUKON-2) */
136 #define PCI_Y2_PHY1_COMA BIT(28) /* Set PHY 1 to Coma Mode (YUKON-2) */
[all …]
|
| /illumos-gate/usr/src/uts/common/io/efe/ |
| H A D | efe.h | 76 #define CSR_NVCTL 0x10 /* Non-volatile Control Register */
226 #define NVCTL_IPG_DLY 7 /* Inter-packet Gap Timer Delay */
229 #define EECTL_EECS (1UL << 1) /* EEPROM Chip Select */
291 #define TXSTAT_ND (1UL << 1) /* Non-deferred Transmission */
313 ddi_get32((efep)->efe_regs_acch, \
314 (efep)->efe_regs + ((reg) / sizeof (uint32_t)))
317 ddi_put32((efep)->efe_regs_acch, \
318 (efep)->efe_regs + ((reg) / sizeof (uint32_t)), (val))
332 #define DESCADDR(rp, x) ((rp)->r_dmac.dmac_address + DESCSZ(x))
333 #define DESCLEN(rp) ((rp)->r_len)
[all …]
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| /illumos-gate/usr/src/uts/common/sys/usb/hcd/ehci/ |
| H A D | ehcid.h | 77 uint16_t ehci_vendor_id; /* chip vendor */
78 uint16_t ehci_device_id; /* chip device */
79 uint8_t ehci_rev_id; /* chip revison */
86 uint_t ehci_frame_interval; /* Frme inter reg */
261 #define EHCI_INTRS_STATS(ehci) ((ehci)->ehci_intrs_stats)
263 ((ehci_intrs_stats_t *)EHCI_INTRS_STATS((ehci))->ks_data)
265 #define EHCI_TOTAL_STATS(ehci) ((ehci)->ehci_total_stats)
266 #define EHCI_TOTAL_STATS_DATA(ehci) (KSTAT_IO_PTR((ehci)->ehci_total_stats))
268 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_CONTROL]))
270 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_BULK]))
[all …]
|