| /freebsd/sys/contrib/device-tree/Bindings/ |
| H A D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
11 control how the core is synthesized. Historically, the EDK tool would
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
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| H A D | example-schema.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 # All the top-level keys are standard json-schema keywords except for
10 $id: http://devicetree.org/schemas/example-schema.yaml#
11 # $schema is the meta-schema this schema should be validated with.
12 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Rob Herring <robh@kernel.org>
20 A more detailed multi-line description of the binding.
44 - items:
51 - enum:
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| /freebsd/sys/contrib/device-tree/Bindings/pwm/ |
| H A D | microchip,corepwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip IP corePWM controller
11 - Conor Dooley <conor.dooley@microchip.com>
14 corePWM is an 16 channel pulse width modulator FPGA IP
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
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| /freebsd/sys/contrib/device-tree/Bindings/media/xilinx/ |
| H A D | video.txt | 1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
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| H A D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
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| /freebsd/sys/contrib/device-tree/Bindings/ptp/ |
| H A D | ptp-ines.txt | 1 ZHAW InES PTP time stamping IP core
3 The IP core needs two different kinds of nodes. The control node
7 port index within the IP core.
11 - compatible: "ines,ptp-ctrl"
12 - reg: physical address and size of the register bank
16 - timestamper: provides control node reference and
17 the port channel within the IP core
22 compatible = "ines,ptp-ctrl";
30 ethernet-phy@3 {
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | allegro.txt | 1 Device-tree bindings for the Allegro DVT video IP codecs present in the Xilinx
2 ZynqMP SoC. The IP core may either be a H.264/H.265 encoder or H.264/H.265
3 decoder ip core.
10 - compatible: value should be one of the following
11 "allegro,al5e-1.1", "allegro,al5e": encoder IP core
12 "allegro,al5d-1.1", "allegro,al5d": decoder IP core
13 - reg: base and length of the memory mapped register region and base and
15 - reg-names: must include "regs" and "sram"
16 - interrupts: shared interrupt from the MCUs to the processing system
17 - clocks: must contain an entry for each entry in clock-names
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| H A D | allegro,al5e.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allegro DVT Video IP Codecs
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
13 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
14 either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.
23 - items:
24 - const: allegro,al5e-1.1
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| H A D | nxp,imx-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
15 receiver IP core named CSIS. The IP core originates from Samsung, and may be
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| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | marvell,xenon-sdhci.txt | 2 This file documents differences between the core mmc properties
5 Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-ap807-sdhci": For controllers on Armada AP807.
16 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
18 - clocks:
20 Require at least input clock for Xenon IP core. For Armada AP806 and
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| H A D | renesas,sdhi.txt | 4 - compatible: should contain one or more of the following:
5 "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
6 "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
7 "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
8 "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
9 "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
10 "renesas,sdhi-r8a7742" - SDHI IP on R8A7742 SoC
11 "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
12 "renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
13 "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
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| H A D | mtk-sd.txt | 6 This file documents differences between the core properties in mmc.txt
10 - compatible: value should be either of the following.
11 "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
12 "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
13 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
14 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
15 "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
16 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
17 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
18 "mediatek,mt7622-mmc": for MT7622 SoC
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| /freebsd/tools/tools/netrate/tcpp/ |
| H A D | parallelism.csh | 4 # Run tcpp -s -p 8 on the server, then this on the client.
6 # Note awkwardly hard-coded IP address below.
16 set nips=4 # Number of local IP addresses to use
17 set baseip=192.168.100.200 # First IP address to use
19 foreach core (`jot $cores`)
21 set mflag=`echo $ptcps / $core | bc`
22 set tflag=`echo $ntcps / $core | bc`
23 echo -n $2,${core},${trial}, >> $1
24 ./tcpp -c 192.168.100.102 -p $core -b $totalbytes -m $mflag \
25 -t $tflag -M $nips -l $baseip >> $1
|
| /freebsd/usr.bin/mail/ |
| H A D | cmd2.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
37 * Mail -- a mail program
54 int *ip, *ip2, list[2], mdot; in next() local
64 mdot = dot - &message[0] + 1; in next()
71 for (ip = msgvec; *ip != 0; ip++) in next()
72 if (*ip > mdot) in next()
74 if (*ip == 0) in next()
75 ip = msgvec; in next()
76 ip2 = ip; in next()
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| /freebsd/sys/contrib/device-tree/Bindings/iio/dac/ |
| H A D | adi,axi-dac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/dac/adi,axi-dac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI DAC IP core
10 - Nuno Sa <nuno.sa@analog.com>
13 Analog Devices Generic AXI DAC IP core for interfacing a DAC device
17 interface for the actual DAC, while this IP core will interface
18 to the data-lines of the DAC and handle the streaming of data from
26 - adi,axi-dac-9.1.b
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | adi,axi-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI ADC IP core
10 - Michael Hennerich <michael.hennerich@analog.com>
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
17 interface for the actual ADC, while this IP core will interface
18 to the data-lines of the ADC and handle the streaming of data into
26 - adi,axi-adc-10.0.a
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| /freebsd/sys/contrib/device-tree/Bindings/input/ |
| H A D | ps2keyb-mouse-apbps2.txt | 1 Aeroflex Gaisler APBPS2 PS/2 Core, supporting Keyboard or Mouse.
3 The APBPS2 PS/2 core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the APBPS2 core, a LEON SPARC system,
11 - name : Should be "GAISLER_APBPS2" or "01_060"
12 - reg : Address and length of the register set for the device
13 - interrupts : Interrupt numbers for this device
15 For further information look in the documentation for the GLIB IP core library:
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | gr-udc.txt | 3 The GRUSBDC USB Device Controller core is available in the GRLIB VHDL
4 IP core library.
6 Note: In the ordinary environment for the core, a Leon SPARC system,
11 - name : Should be "GAISLER_USBDC" or "01_021"
13 - reg : Address and length of the register set for the device
15 - interrupts : Interrupt numbers for this device. Either one interrupt number
21 - epobufsizes : Array of buffer sizes for OUT endpoints when they differ
24 each OUT endpoint of the core. Fewer entries overrides the default sizes
27 - epibufsizes : Array of buffer sizes for IN endpoints when they differ
30 each IN endpoint of the core. Fewer entries overrides the default sizes
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| H A D | amlogic,meson-g12a-usb-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-grgpio.txt | 3 The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the GRGPIO core, a Leon SPARC system,
10 - name : Should be "GAISLER_GPIO" or "01_01a"
12 - reg : Address and length of the register set for the device
14 - interrupts : Interrupt numbers for this device
18 - nbits : The number of gpio lines. If not present driver assumes 32 lines.
20 - irqmap : An array with an index for each gpio line. An index is either a valid
25 For further information look in the documentation for the GLIB IP core library:
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| /freebsd/sys/contrib/device-tree/Bindings/i2c/ |
| H A D | i2c-demux-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-demux-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Pinctrl-based I2C Bus Demultiplexer
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
16 IP core at runtime which may have a better feature set for a given task than
17 another I2C IP core on the SoC. The most simple example is to fall back to
19 internal IP core.
21 +-------------------------------+
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| H A D | i2c-demux-pinctrl.txt | 1 Pinctrl-based I2C Bus DeMux
5 the pinctrl device tree bindings. This may be used to select one I2C IP core at
7 IP core on the SoC. The most simple example is to fall back to GPIO bitbanging
8 if your current runtime configuration hits an errata of the internal IP core.
10 +-------------------------------+
12 | | +-----+ +-----+
13 | +------------+ | | dev | | dev |
14 | |I2C IP Core1|--\ | +-----+ +-----+
15 | +------------+ \-------+ | | |
16 | |Pinctrl|--|------+--------+
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| /freebsd/lib/libc/net/ |
| H A D | protocols | 3 # See also http://www.iana.org/assignments/protocol-numbers
5 ip 0 IP # internet protocol, pseudo protocol number
6 #hopopt 0 HOPOPT # hop-by-hop options for ipv6
9 ggp 3 GGP # gateway-gateway protocol
10 ipencap 4 IP-ENCAP # IP encapsulated in IP (officially ``IP'')
16 bbn-rcc 10 BBN-RCC-MON # BBN RCC Monitoring
17 nvp 11 NVP-II # Network Voice Protocol
25 dcn 19 DCN-MEAS # DCN Measurement Subsystems
28 xns-idp 22 XNS-IDP # Xerox NS IDP
29 trunk-1 23 TRUNK-1 # Trunk-1
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| /freebsd/contrib/processor-trace/libipt/include/ |
| H A D | intel-pt.h | 2 * Copyright (c) 2013-2019, Intel Corporation
44 * - Version
45 * - Errors
46 * - Configuration
47 * - Packet encoder / decoder
48 * - Query decoder
49 * - Traced image
50 * - Instruction flow decoder
51 * - Block decoder
151 /* There is no IP. */
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| H A D | intel-pt.h.in | 2 * Copyright (c) 2013-2019, Intel Corporation
44 * - Version
45 * - Errors
46 * - Configuration
47 * - Packet encoder / decoder
48 * - Query decoder
49 * - Traced image
50 * - Instruction flow decoder
51 * - Block decoder
151 /* There is no IP. */
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