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/linux/tools/testing/selftests/net/
H A Drps_default_mask.sh2 # SPDX-License-Identifier: GPL-2.0
8 [ $cpus -gt 2 ] || exit $ksft_skip
10 readonly INITIAL_RPS_DEFAULT_MASK=$(cat /proc/sys/net/core/rps_default_mask)
11 readonly TAG="$(mktemp -u XXXXXX)"
13 readonly NETNS="ns-${TAG}"
16 ip netns add "${NETNS}"
17 ip -netn
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H A Dnetns-sysctl.sh1 #!/bin/bash -e
2 # SPDX-License-Identifier: GPL-2.0
24 [ -w "/proc/sys/net/core/$sc" ] ||
28 sysctl -qw "net.core.$sc=300000" ||
32 [ "$(ip netns exec $test_ns sysctl -n "net.core.$sc")" -eq 300000 ] ||
36 ip netns exec $test_ns [ -w "/proc/sys/net/core/$sc" ] &&
/linux/drivers/net/can/ctucanfd/
H A DKconfig2 tristate "CTU CAN-FD IP core" if COMPILE_TEST
4 This driver adds support for the CTU CAN FD open-source IP core.
5 More documentation and core sources at project page
7 The core integration to Xilinx Zynq system as platform driver
8 is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top).
9 Implementation on Intel FPGA-based PCI Express board is available
10 from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd) and
11 on Intel SoC from project (https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd).
15 tristate "CTU CAN-FD IP core PCI/PCIe driver"
19 This driver adds PCI/PCIe support for CTU CAN-FD IP core.
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/linux/Documentation/devicetree/bindings/pwm/
H A Dmicrochip,corepwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip IP corePWM controller
11 - Conor Dooley <conor.dooley@microchip.com>
14 corePWM is an 16 channel pulse width modulator FPGA IP
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
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/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dvideo.txt1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
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H A Dxlnx,video.txt1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
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/linux/drivers/staging/axis-fifo/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
/linux/Documentation/driver-api/
H A Dxillybus.rst10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
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/linux/Documentation/devicetree/bindings/ptp/
H A Dptp-ines.txt1 ZHAW InES PTP time stamping IP core
3 The IP core needs two different kinds of nodes. The control node
7 port index within the IP core.
11 - compatible: "ines,ptp-ctrl"
12 - reg: physical address and size of the register bank
16 - timestamper: provides control node reference and
17 the port channel within the IP core
22 compatible = "ines,ptp-ctrl";
30 ethernet-phy@3 {
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dadi,axi-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI ADC IP core
10 - Michael Hennerich <michael.hennerich@analog.com>
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
17 interface for the actual ADC, while this IP core will interface
18 to the data-lines of the ADC and handle the streaming of data into
24 IP core's name.
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/linux/Documentation/devicetree/bindings/media/
H A Dallegro,al5e.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allegro DVT Video IP Codecs
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
13 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
14 either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.
23 - items:
24 - const: allegro,al5e-1.1
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/linux/fs/xfs/libxfs/
H A Dxfs_metafile.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2018-2024 Oracle. All Rights Reserved.
50 struct xfs_inode *ip, in xfs_metafile_set_iflag() argument
53 VFS_I(ip)->i_mode &= ~0777; in xfs_metafile_set_iflag()
54 VFS_I(ip) in xfs_metafile_set_iflag()
73 xfs_metafile_clear_iflag(struct xfs_trans * tp,struct xfs_inode * ip) xfs_metafile_clear_iflag() argument
135 xfs_metafile_resv_alloc_space(struct xfs_inode * ip,struct xfs_alloc_arg * args) xfs_metafile_resv_alloc_space() argument
192 xfs_metafile_resv_free_space(struct xfs_inode * ip,struct xfs_trans * tp,xfs_filblks_t len) xfs_metafile_resv_free_space() argument
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/linux/Documentation/devicetree/bindings/input/
H A Dps2keyb-mouse-apbps2.txt1 Aeroflex Gaisler APBPS2 PS/2 Core, supporting Keyboard or Mouse.
3 The APBPS2 PS/2 core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the APBPS2 core, a LEON SPARC system,
11 - name : Should be "GAISLER_APBPS2" or "01_060"
12 - reg : Address and length of the register set for the device
13 - interrupts : Interrupt numbers for this device
15 For further information look in the documentation for the GLIB IP core library:
/linux/drivers/fpga/
H A Daltera-pr-ip-core-plat.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Altera Partial Reconfiguration IP Core
5 * Copyright (C) 2016-2017 Intel Corporation
7 * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
10 #include <linux/fpga/altera-pr-ip-core.h>
16 struct device *dev = &pdev->dev; in alt_pr_platform_probe()
28 { .compatible = "altr,a10-pr-ip", },
44 MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Platform Driver");
/linux/arch/arm/mach-bcm/
H A Dbcm_kona_smc.c1 // SPDX-License-Identifier: GPL-2.0-only
25 {.compatible = "brcm,kona-smc"},
26 {.compatible = "bcm,kona-smc"}, /* deprecated name */
40 return -ENODEV; in bcm_kona_smc_init()
45 return -EINVAL; in bcm_kona_smc_init()
49 return -ENOMEM; in bcm_kona_smc_init()
60 * Only core 0 can run the secure monitor code. If an "smc" request
61 * is initiated on a different core it must be redirected to core 0
69 * Parameters to the "smc" request are passed in r4-r6 as follows:
89 register u32 ip asm("ip"); /* Also called r12 */ in bcm_kona_do_smc()
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/linux/tools/perf/Documentation/
H A Dperf-amd-ibs.txt1 perf-amd-ibs(1)
5 ----
6 perf-amd-ibs - Support for AMD Instruction-Base
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/linux/drivers/mcb/
H A Dmcb-internal.h1 /* SPDX-License-Identifier: GPL-2.0 */
51 * struct chameleon_gdd - Chameleon General Device Descriptor
55 * @var: the variant of the IP core
56 * @dev: the device the IP core is
86 * struct chameleon_bdd - Chameleon Bridge Device Descriptor
90 * @var: the variant of the IP core
91 * @dev: the device the IP core is
/linux/Documentation/devicetree/bindings/usb/
H A Dgr-udc.txt3 The GRUSBDC USB Device Controller core is available in the GRLIB VHDL
4 IP core library.
6 Note: In the ordinary environment for the core, a Leon SPARC system,
11 - name : Should be "GAISLER_USBDC" or "01_021"
13 - reg : Address and length of the register set for the device
15 - interrupts : Interrupt numbers for this device. Either one interrupt number
21 - epobufsizes : Array of buffer sizes for OUT endpoints when they differ
24 each OUT endpoint of the core. Fewer entries overrides the default sizes
27 - epibufsizes : Array of buffer sizes for IN endpoints when they differ
30 each IN endpoint of the core. Fewer entries overrides the default sizes
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H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
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/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-grgpio.txt3 The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the GRGPIO core, a Leon SPARC system,
10 - name : Should be "GAISLER_GPIO" or "01_01a"
12 - reg : Address and length of the register set for the device
14 - interrupts : Interrupt numbers for this device
18 - nbits : The number of gpio lines. If not present driver assumes 32 lines.
20 - irqmap : An array with an index for each gpio line. An index is either a valid
25 For further information look in the documentation for the GLIB IP core library:
/linux/tools/perf/util/
H A Dintel-pt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2013-2015, Intel Corporation.
28 #include "thread-stack.h"
35 #include "intel-pt.h"
38 #include "util/synthetic-events.h"
39 #include "time-utils.h"
43 #include "intel-p
669 intel_pt_guest_kernel_ip(uint64_t ip) intel_pt_guest_kernel_ip() argument
675 intel_pt_nr_cpumode(struct intel_pt_queue * ptq,uint64_t ip,bool nr) intel_pt_nr_cpumode() argument
749 intel_pt_walk_next_insn(struct intel_pt_insn * intel_pt_insn,uint64_t * insn_cnt_ptr,uint64_t * ip,uint64_t to_ip,uint64_t max_insn_cnt,void * data) intel_pt_walk_next_insn() argument
947 intel_pt_match_pgd_ip(struct intel_pt * pt,uint64_t ip,uint64_t offset,const char * filename) intel_pt_match_pgd_ip() argument
985 __intel_pt_pgd_ip(uint64_t ip,void * data) __intel_pt_pgd_ip() argument
1020 intel_pt_pgd_ip(uint64_t ip,void * data) intel_pt_pgd_ip() argument
2685 intel_pt_synth_error(struct intel_pt * pt,int code,int cpu,pid_t pid,pid_t tid,u64 ip,u64 timestamp,pid_t machine_pid,int vcpu) intel_pt_synth_error() argument
2771 intel_pt_is_switch_ip(struct intel_pt_queue * ptq,u64 ip) intel_pt_is_switch_ip() argument
2966 u64 ip, switch_ip = 0; intel_pt_switch_ip() local
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/linux/drivers/media/platform/allegro-dvt/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Allegro DVT Video IP Core"
14 Support for the encoder video IP core by Allegro DVT. This core is
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4_core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * HDMI header definition for OMAP4 HDMI core IP
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
13 /* OMAP4 HDMI IP Core System */
91 /* HDMI DDC E-DID */
101 /* HDMI IP Core Audio Video */
252 int hdmi4_core_ddc_init(struct hdmi_core_data *core);
255 void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
257 void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s);
258 int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core);
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/linux/Documentation/devicetree/bindings/clock/
H A Daxis,artpec8-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Axis ARTPEC-8 SoC clock controller
10 - Jesper Nilsson <jesper.nilsson@axis.com>
13 ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
17 This external clock must be defined as a fixed-rate clock in dts.
19 CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
26 'include/dt-bindings/clock/axis,artpec8-clk.h' header.
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/linux/tools/perf/pmu-events/arch/x86/clearwaterforest/
H A Dpipeline.json41 "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for. Available PDIST counters: 0,1",
254 "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. Available PDIST counters: 0,1",
314 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
316 "EventName": "CPU_CLK_UNHALTED.CORE",
321 "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
339 "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enter
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