| /linux/tools/testing/selftests/net/ |
| H A D | rps_default_mask.sh | 2 # SPDX-License-Identifier: GPL-2.0
8 [ $cpus -gt 2 ] || exit $ksft_skip
10 readonly INITIAL_RPS_DEFAULT_MASK=$(cat /proc/sys/net/core/rps_default_mask)
11 readonly TAG="$(mktemp -u XXXXXX)"
13 readonly NETNS="ns-${TAG}"
16 ip netns add "${NETNS}"
17 ip -netn
[all...] |
| /linux/drivers/net/can/ctucanfd/ |
| H A D | Kconfig | 2 tristate "CTU CAN-FD IP core" if COMPILE_TEST
4 This driver adds support for the CTU CAN FD open-source IP core.
5 More documentation and core sources at project page
7 The core integration to Xilinx Zynq system as platform driver
8 is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top).
9 Implementation on Intel FPGA-based PCI Express board is available
10 from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd) and
11 on Intel SoC from project (https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd).
15 tristate "CTU CAN-FD IP core PCI/PCIe driver"
19 This driver adds PCI/PCIe support for CTU CAN-FD IP core.
[all …]
|
| /linux/Documentation/devicetree/bindings/pwm/ |
| H A D | microchip,corepwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip IP corePWM controller
11 - Conor Dooley <conor.dooley@microchip.com>
14 corePWM is an 16 channel pulse width modulator FPGA IP
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
[all …]
|
| /linux/Documentation/devicetree/bindings/media/xilinx/ |
| H A D | video.txt | 1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
[all …]
|
| H A D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
[all …]
|
| /linux/drivers/staging/axis-fifo/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
|
| /linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
[all …]
|
| /linux/Documentation/devicetree/bindings/ptp/ |
| H A D | ptp-ines.txt | 1 ZHAW InES PTP time stamping IP core
3 The IP core needs two different kinds of nodes. The control node
7 port index within the IP core.
11 - compatible: "ines,ptp-ctrl"
12 - reg: physical address and size of the register bank
16 - timestamper: provides control node reference and
17 the port channel within the IP core
22 compatible = "ines,ptp-ctrl";
30 ethernet-phy@3 {
|
| /linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | adi,axi-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI ADC IP core
10 - Michael Hennerich <michael.hennerich@analog.com>
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
17 interface for the actual ADC, while this IP core will interface
18 to the data-lines of the ADC and handle the streaming of data into
24 IP core's name.
[all …]
|
| /linux/drivers/usb/usbip/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 tristate "USB/IP support"
9 This enables pushing USB packets over IP to allow remote
11 USB/IP core that is required by both drivers.
17 be called usbip-core.
25 This enables the USB/IP virtual host controller driver,
29 module will be called vhci-hcd.
32 int "Number of ports per USB/IP virtual host controller"
37 To increase number of ports available for USB/IP virtual
39 USB/IP virtual host controller.
[all …]
|
| /linux/Documentation/devicetree/bindings/media/ |
| H A D | allegro,al5e.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allegro DVT Video IP Codecs
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
13 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
14 either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.
23 - items:
24 - const: allegro,al5e-1.1
[all …]
|
| /linux/drivers/pci/controller/dwc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
37 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
38 core plus Annapurna Labs proprietary hardware wrappers. This is
39 required only for DT-based platforms. ACPI platforms with the
50 DesignWare IP and therefore the driver re-uses the DesignWare
51 core functions to implement the driver.
61 and therefore the driver re-uses the DesignWare core functions to
68 bool "Axis ARTPEC-6 PCIe controller (host mode)"
74 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
[all …]
|
| /linux/fs/xfs/libxfs/ |
| H A D | xfs_metafile.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2018-2024 Oracle. All Rights Reserved.
50 struct xfs_inode *ip, in xfs_metafile_set_iflag() argument
53 VFS_I(ip)->i_mode &= ~0777; in xfs_metafile_set_iflag()
54 VFS_I(ip)->i_uid = GLOBAL_ROOT_UID; in xfs_metafile_set_iflag()
55 VFS_I(ip)->i_gid = GLOBAL_ROOT_GID; in xfs_metafile_set_iflag()
56 if (S_ISDIR(VFS_I(ip)->i_mode)) in xfs_metafile_set_iflag()
57 ip->i_diflags |= XFS_METADIR_DIFLAGS; in xfs_metafile_set_iflag()
59 ip->i_diflags |= XFS_METAFILE_DIFLAGS; in xfs_metafile_set_iflag()
60 ip->i_diflags2 &= ~XFS_DIFLAG2_DAX; in xfs_metafile_set_iflag()
[all …]
|
| /linux/Documentation/networking/caif/ |
| H A D | linux_caif.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 Copyright |copy| ST-Ericsson AB 2010
17 CAIF is a MUX protocol used by ST-Ericsson cellular modems for
22 ST-Ericsson modems support a number of transports between modem
31 * CAIF Socket Layer and GPRS IP Interface.
32 * CAIF Core Protocol Implementation
39 ! +------+ +------+
40 ! +------+! +------+!
41 ! ! IP !! !Socket!!
42 +-------> !interf!+ ! API !+ <- CAIF Client APIs
[all …]
|
| /linux/Documentation/devicetree/bindings/input/ |
| H A D | ps2keyb-mouse-apbps2.txt | 1 Aeroflex Gaisler APBPS2 PS/2 Core, supporting Keyboard or Mouse.
3 The APBPS2 PS/2 core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the APBPS2 core, a LEON SPARC system,
11 - name : Should be "GAISLER_APBPS2" or "01_060"
12 - reg : Address and length of the register set for the device
13 - interrupts : Interrupt numbers for this device
15 For further information look in the documentation for the GLIB IP core library:
|
| /linux/arch/arm/mach-bcm/ |
| H A D | bcm_kona_smc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 {.compatible = "brcm,kona-smc"},
26 {.compatible = "bcm,kona-smc"}, /* deprecated name */
40 return -ENODEV; in bcm_kona_smc_init()
45 return -EINVAL; in bcm_kona_smc_init()
49 return -ENOMEM; in bcm_kona_smc_init()
60 * Only core 0 can run the secure monitor code. If an "smc" request
61 * is initiated on a different core it must be redirected to core 0
69 * Parameters to the "smc" request are passed in r4-r6 as follows:
89 register u32 ip asm("ip"); /* Also called r12 */ in bcm_kona_do_smc()
[all …]
|
| /linux/drivers/fpga/ |
| H A D | altera-pr-ip-core-plat.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Altera Partial Reconfiguration IP Core
5 * Copyright (C) 2016-2017 Intel Corporation
7 * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
10 #include <linux/fpga/altera-pr-ip-core.h>
17 struct device *dev = &pdev->dev; in alt_pr_platform_probe()
29 { .compatible = "altr,a10-pr-ip", },
45 MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Platform Driver");
|
| /linux/tools/perf/Documentation/ |
| H A D | perf-amd-ibs.txt | 1 perf-amd-ibs(1)
5 ----
6 perf-amd-ibs - Support for AMD Instruction-Based Sampling (IBS) with perf tool
9 --------
11 'perf record' -e ibs_op//
12 'perf record' -e ibs_fetch//
15 -----------
17 Instruction-Based Sampling (IBS) provides precise Instruction Pointer (IP)
20 execution (micro-op execution to be precise) with details like d-cache
21 hit/miss, d-TLB hit/miss, cache miss latency, load/store data source, branch
[all …]
|
| /linux/drivers/mcb/ |
| H A D | mcb-internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
51 * struct chameleon_gdd - Chameleon General Device Descriptor
55 * @var: the variant of the IP core
56 * @dev: the device the IP core is
86 * struct chameleon_bdd - Chameleon Bridge Device Descriptor
90 * @var: the variant of the IP core
91 * @dev: the device the IP core is
|
| /linux/tools/perf/util/ |
| H A D | intel-pt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2013-2015, Intel Corporation.
28 #include "thread-stack.h"
35 #include "intel-pt.h"
38 #include "util/synthetic-events.h"
39 #include "time-utils.h"
43 #include "intel-pt-decoder/intel-pt-log.h"
44 #include "intel-pt-decoder/intel-pt-decoder.h"
45 #include "intel-pt-decoder/intel-pt-insn-decoder.h"
46 #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
[all …]
|
| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | gr-udc.txt | 3 The GRUSBDC USB Device Controller core is available in the GRLIB VHDL
4 IP core library.
6 Note: In the ordinary environment for the core, a Leon SPARC system,
11 - name : Should be "GAISLER_USBDC" or "01_021"
13 - reg : Address and length of the register set for the device
15 - interrupts : Interrupt numbers for this device. Either one interrupt number
21 - epobufsizes : Array of buffer sizes for OUT endpoints when they differ
24 each OUT endpoint of the core. Fewer entries overrides the default sizes
27 - epibufsizes : Array of buffer sizes for IN endpoints when they differ
30 each IN endpoint of the core. Fewer entries overrides the default sizes
[all …]
|
| H A D | amlogic,meson-g12a-usb-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
[all …]
|
| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-grgpio.txt | 3 The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the GRGPIO core, a Leon SPARC system,
10 - name : Should be "GAISLER_GPIO" or "01_01a"
12 - reg : Address and length of the register set for the device
14 - interrupts : Interrupt numbers for this device
18 - nbits : The number of gpio lines. If not present driver assumes 32 lines.
20 - irqmap : An array with an index for each gpio line. An index is either a valid
25 For further information look in the documentation for the GLIB IP core library:
|
| /linux/Documentation/devicetree/bindings/i2c/ |
| H A D | i2c-demux-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-demux-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Pinctrl-based I2C Bus Demultiplexer
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
16 IP core at runtime which may have a better feature set for a given task than
17 another I2C IP core on the SoC. The most simple example is to fall back to
19 internal IP core.
21 +-------------------------------+
[all …]
|
| /linux/drivers/gpu/drm/xlnx/ |
| H A D | zynqmp_dp.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
27 #include <linux/media-bus-format.h>
74 /* Core enable registers */
90 /* Core ID registers */
249 * struct zynqmp_dp_link_config - Common link config between source and sink
259 * struct zynqmp_dp_mode - Configured mode of DisplayPort
273 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
[all …]
|