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Searched full:iomuxc_gpr1 (Results 1 – 8 of 8) sorted by relevance

/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dfsl,imx-weim.yaml63 WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
67 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
75 sets up in IOMUXC_GPR1[11:0] will be used.
/linux/arch/arm/mach-imx/
H A Dmach-imx6sl.c25 regmap_update_bits(gpr, IOMUXC_GPR1, in imx6sl_fec_init()
27 regmap_update_bits(gpr, IOMUXC_GPR1, in imx6sl_fec_init()
H A Dmach-imx7d.c44 regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); in imx7d_enet_clk_sel()
45 regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); in imx7d_enet_clk_sel()
H A Dmach-imx6q.c115 * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad in imx6q_1588_init()
123 regmap_update_bits(gpr, IOMUXC_GPR1, in imx6q_1588_init()
/linux/include/linux/mfd/syscon/
H A Dimx7-iomuxc-gpr.h10 #define IOMUXC_GPR1 0x04 macro
H A Dimx6q-iomuxc-gpr.h12 #define IOMUXC_GPR1 0x04 macro
/linux/drivers/clk/imx/
H A Dclk-imx6ul.c491 IOMUXC_GPR1, enet1_ref_sels, ARRAY_SIZE(enet1_ref_sels), in imx6ul_clocks_init()
496 IOMUXC_GPR1, enet2_ref_sels, ARRAY_SIZE(enet2_ref_sels), in imx6ul_clocks_init()
/linux/sound/soc/fsl/
H A Dfsl_sai.c1629 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), in fsl_sai_probe()