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/linux/Documentation/devicetree/bindings/sound/
H A Drockchip,i2s-tdm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip I2S/TDM Controller
10 The Rockchip I2S/TDM Controller is a Time Division Multiplexed
15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
18 - $ref: dai-common.yaml#
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
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H A Dallwinner,sun4i-a10-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 I2S Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#sound-dai-cells":
19 - const: allwinner,sun4i-a10-i2s
20 - const: allwinner,sun6i-a31-i2s
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H A Dsnps,designware-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare I2S controller
10 - Jose Abreu <joabreu@synopsys.com>
15 - items:
16 - const: canaan,k210-i2s
17 - const: snps,designware-i2s
18 - enum:
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H A Dingenic,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs AC97 / I2S Controller (AIC)
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: dai-common.yaml#
17 pattern: '^audio-controller@'
21 - enum:
22 - ingenic,jz4740-i2s
23 - ingenic,jz4760-i2s
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H A Dintel,keembay-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/sound/intel,keembay-i2s.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel KeemBay I2S
11 - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
12 - Paul J. Murphy <paul.j.murphy@intel.com>
15 Intel KeemBay I2S
18 - $ref: dai-common.yaml#
23 - intel,keembay-i2s
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H A Drockchip-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip I2S controller
10 The I2S bus (Inter-IC sound bus) is a serial link for digital
14 - Heiko Stuebner <heiko@sntech.de>
17 - $ref: dai-common.yaml#
22 - const: rockchip,rk3066-i2s
23 - items:
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H A Dsamsung-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC I2S controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - $ref: dai-common.yaml#
19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
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H A Dimg,i2s-in.txt1 Imagination Technologies I2S Input Controller
5 - compatible : Compatible list, must contain "img,i2s-in"
7 - #sound-dai-cells : Must be equal to 0
9 - reg : Offset and length of the register set for the device
11 - clocks : Contains an entry for each entry in clock-names
13 - clock-names : Must include the following entry:
16 - dmas: Contains an entry for each entry in dma-names.
18 - dma-names: Must include the following entry:
19 "rx" Single DMA channel used by all active I2S channels
21 - img,i2s-channels : Number of I2S channels instantiated in the I2S in block
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H A Dnxp,lpc3220-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nxp,lpc3220-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP LPC32XX I2S Controller
10 The I2S controller in LPC32XX SoCs, ASoC DAI.
13 - J.M.B. Downing <jonathan.downing@nautel.com>
14 - Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
17 - $ref: dai-common.yaml#
22 - nxp,lpc3220-i2s
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H A Datmel,sama5d2-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/sound/atmel,sama5d2-i2s.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Atmel I2S controller
11 - Nicolas Ferre <nicolas.ferre@microchip.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 Atmel I2S (Inter-IC Sound Controller) bus is the standard
21 const: atmel,sama5d2-i2s
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H A Dhisilicon,hi6210-i2s.txt1 * Hisilicon 6210 i2s controller
5 - compatible: should be one of the following:
6 - "hisilicon,hi6210-i2s"
7 - reg: physical base address of the i2s controller unit and length of
9 - interrupts: should contain the i2s interrupt.
10 - clocks: a list of phandle + clock-specifier pairs, one for each entry
11 in clock-names.
12 - clock-names: should contain following:
13 - "dacodec"
14 - "i2s-base"
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H A Dnvidia,tegra20-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 I2S Controller
10 The I2S Controller streams synchronous serial audio data between system
11 memory and an external audio device. The controller supports the I2S Left
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
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H A Dst,stm32-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/st,stm32-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 SPI/I2S Controller
10 - Olivier Moysan <olivier.moysan@foss.st.com>
13 The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode.
14 Only some SPI instances support I2S.
17 - $ref: dai-common.yaml#
22 - st,stm32h7-i2s
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H A Dadi,axi-i2s.txt1 ADI AXI-I2S controller
7 - compatible : Must be "adi,axi-i2s-1.00.a"
8 - reg : Must contain I2S core's registers location and length
9 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
14 - dmas: Pairs of phandle and specifier for the DMA channels that are used by
17 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
19 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
21 * resource-names.txt
22 * clock/clock-bindings.txt
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H A Dbrcm,bcm2835-i2s.txt1 * Broadcom BCM2835 SoC I2S/PCM module
4 - compatible: "brcm,bcm2835-i2s"
5 - reg: Should contain PCM registers location and length.
6 - clocks: the (PCM) clock to use
7 - dmas: List of DMA controller phandle and DMA request line ordered pairs.
8 - dma-names: Identifier string for each DMA request line in the dmas property.
12 named "tx") and one for reception (should be named "rx").
16 bcm2835_i2s: i2s@7e203000 {
17 compatible = "brcm,bcm2835-i2s";
23 dma-names = "tx", "rx";
/linux/sound/soc/loongson/
H A Dloongson_i2s.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ALSA I2S interface for the Loongson platform
15 /* I2S Common Registers */
16 #define LS_I2S_VER 0x00 /* I2S Version */
17 #define LS_I2S_CFG 0x04 /* I2S Config */
18 #define LS_I2S_CTRL 0x08 /* I2S Control */
19 #define LS_I2S_RX_DATA 0x0C /* I2S DMA RX Address */
20 #define LS_I2S_TX_DATA 0x10 /* I2S DMA TX Address */
22 /* 2K2000 I2S Specify Registers */
23 #define LS_I2S_CFG1 0x14 /* I2S Config1 */
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H A Dloongson_i2s_pci.c1 // SPDX-License-Identifier: GPL-2.0
3 // loongson_i2s_pci.c -- Loongson I2S controller driver
12 #include <linux/dma-mapping.h>
76 const struct fwnode_handle *fwnode = pdev->dev.fwnode; in loongson_i2s_pci_probe()
78 struct device *dev = &pdev->dev; in loongson_i2s_pci_probe()
79 struct loongson_i2s *i2s; in loongson_i2s_pci_probe() local
84 return -ENODEV; in loongson_i2s_pci_probe()
87 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); in loongson_i2s_pci_probe()
88 if (!i2s) in loongson_i2s_pci_probe()
89 return -ENOMEM; in loongson_i2s_pci_probe()
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/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-syscrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-syscrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC1 RMII reference or GMAC1 RGMII RX
24 - description: External I2S TX bit clock
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/linux/sound/soc/qcom/qdsp6/
H A Dq6prm.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Clock ID for Primary I2S IBIT */
8 /* Clock ID for Primary I2S EBIT */
10 /* Clock ID for Secondary I2S IBIT */
12 /* Clock ID for Secondary I2S EBIT */
14 /* Clock ID for Tertiary I2S IBIT */
16 /* Clock ID for Tertiary I2S EBIT */
18 /* Clock ID for Quartnery I2S IBIT */
20 /* Clock ID for Quartnery I2S EBIT */
22 /* Clock ID for Speaker I2S IBIT */
[all …]
/linux/sound/soc/pxa/
H A Dpxa2xx-i2s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pxa2xx-i2s.c -- ALSA Soc Audio Layer
21 #include <sound/pxa2xx-lib.h>
24 #include <linux/platform_data/asoc-pxa.h>
26 #include "pxa2xx-i2s.h"
29 * I2S Controller Register and Bit Definitions
32 #define SACR1 (0x0004) /* Serial Audio I 2 S/MSB-Justified Control Register */
33 #define SASR0 (0x000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
37 #define SADR (0x0080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
39 #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
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/linux/sound/soc/codecs/
H A Drk817_codec.c1 // SPDX-License-Identifier: GPL-2.0
32 * I don't have another implementation to compare from the Rockchip sources. Hard-coding for now.
45 if (rk817->mic_in_differential) { in rk817_init()
61 /* Set the PLL pre-divide value (values not documented). */ in rk817_set_component_pll()
73 * 0db~-95db, 0.375db/step, for example:
75 * 0xff: -95dB
78 static const DECLARE_TLV_DB_MINMAX(rk817_vol_tlv, -9500, 0);
82 * 27db~-18db, 3db/step, for example:
83 * 0x0: -18dB
87 static const DECLARE_TLV_DB_MINMAX(rk817_gain_tlv, -1800, 2700);
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/linux/arch/arm/mach-s3c/
H A Dpl080.c1 // SPDX-License-Identifier: GPL-2.0
3 // Samsung's S3C64XX generic DMA support using amba-pl08x driver.
17 #include "regs-sys-s3c64xx.h"
21 return cd->min_signal; in pl08x_get_xfer_signal()
117 { "s3c6400-uart.0", "tx", &s3c64xx_dma0_info[0] },
118 { "s3c6400-uart.0", "rx", &s3c64xx_dma0_info[1] },
119 { "s3c6400-uart.1", "tx", &s3c64xx_dma0_info[2] },
120 { "s3c6400-uart.1", "rx", &s3c64xx_dma0_info[3] },
121 { "s3c6400-uart.2", "tx", &s3c64xx_dma0_info[4] },
122 { "s3c6400-uart.2", "rx", &s3c64xx_dma0_info[5] },
[all …]
/linux/sound/soc/tegra/
H A Dtegra210_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra210_i2s.c - Tegra210 I2S driver
33 * is required to select i2s4b for it to be functional for I2S
44 regmap_write(regmap, TEGRA210_I2S_SLOT_CTRL, total_slots - 1); in tegra210_i2s_set_slot_ctrl()
52 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_set_clock_rate() local
56 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val); in tegra210_i2s_set_clock_rate()
58 /* No need to set rates if I2S is being operated in slave */ in tegra210_i2s_set_clock_rate()
62 err = clk_set_rate(i2s->clk_i2s, clock_rate); in tegra210_i2s_set_clock_rate()
64 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n", in tegra210_i2s_set_clock_rate()
69 if (!IS_ERR(i2s->clk_sync_input)) { in tegra210_i2s_set_clock_rate()
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/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-suniv-f1c100s.c2 * Allwinner new F-series F1C100s SoC (suniv) pinctrl driver.
12 * Copyright (C) 2014 Chen-Yu Tsai
14 * Chen-Yu Tsai <wens@csie.org>
18 * Maxime Ripard <maxime.ripard@free-electrons.com>
30 #include "pinctrl-sunxi.h"
36 SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
43 SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
51 SUNXI_FUNCTION(0x4, "i2s"), /* IN */
52 SUNXI_FUNCTION(0x5, "uart1"), /* RX */
58 SUNXI_FUNCTION(0x3, "ir0"), /* RX */
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
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