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/linux/drivers/media/platform/verisilicon/
H A Dhantro_v4l2.h3 * Hantro VPU codec driver
19 #include "hantro.h"
H A Dhantro_g1.c3 * Hantro VPU codec driver
11 #include "hantro.h"
H A Dhantro_mpeg2.c3 * Hantro VPU codec driver
8 #include "hantro.h"
H A Dsama5d4_vdec_hw.c3 * Hantro VDEC driver
8 #include "hantro.h"
H A Dsunxi_vpu_hw.c3 * Allwinner Hantro G2 VPU codec driver
10 #include "hantro.h"
H A Dhantro_h1_jpeg_enc.c3 * Hantro VPU codec driver
11 #include "hantro.h"
H A Drockchip_vpu2_hw_jpeg_enc.c3 * Hantro VPU codec driver
28 #include "hantro.h"
H A Dhantro_vp9.c3 * Hantro VP9 codec driver
11 #include "hantro.h"
H A Dhantro_vp8.c3 * Hantro VPU codec driver
8 #include "hantro.h"
H A Dimx8m_vpu_hw.c3 * Hantro VPU codec driver
11 #include "hantro.h"
H A Dhantro_g1_mpeg2_dec.c3 * Hantro VPU codec driver
11 #include "hantro.h"
H A Drockchip_vpu2_hw_mpeg2_dec.c3 * Hantro VPU codec driver
11 #include "hantro.h"
H A Dhantro_vp9.h3 * Hantro VP9 codec driver
H A Dstm32mp25_vpu_hw.c11 #include "hantro.h"
H A Dhantro.h3 * Hantro VPU codec driver
139 * struct hantro_func - Hantro VPU functionality
H A Dhantro_jpeg.c16 #include "hantro.h"
171 "Hantro JPEG header size needs to be 8-byte aligned.");
H A Dhantro_g1_vp8_dec.c3 * Hantro VP8 codec driver
15 #include "hantro.h"
H A Dhantro_h1_regs.h3 * Hantro VPU codec driver
H A Dhantro_h264.c17 #include "hantro.h"
482 * Reduce ref lists to at most 16 entries, Hantro hardware will deduce in hantro_h264_dec_prepare_run()
H A Dhantro_g2_vp9_dec.c3 * Hantro VP9 codec driver
15 #include "hantro.h"
H A Drockchip_vpu2_hw_vp8_dec.c18 #include "hantro.h"
/linux/Documentation/devicetree/bindings/media/
H A Dmicrochip,sama5d4-vdec.yaml8 title: Hantro G1 VPU codec implemented on Microchip SAMA5D4 SoCs
14 Hantro G1 video decode accelerator present on Microchip SAMA5D4 SoCs.
H A Dst,stm32mp25-video-codec.yaml14 decoder peripheral based on Verisilicon VC8000NanoD IP (former Hantro G1)
16 VC8000NanoE IP (former Hantro H1).
H A Dallwinner,sun50i-h6-vpu-g2.yaml8 title: Hantro G2 VPU codec implemented on Allwinner H6 SoC
14 Hantro G2 video decode accelerator present on Allwinner H6 SoC.
H A Dnxp,imx8mq-vpu.yaml8 title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs
14 Hantro G1/G2 video decode accelerators present on i.MX8MQ SoCs.

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