HS\-PHY (full) in projects: freebsd - OpenGrok search results

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Searched +full:hs +full:- +full:phy (Results 1 – 25 of 192) sorted by relevance

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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A D	qcom,usb-snps-femto-v2.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Synopsys Femto High-Speed USB PHY V2 10 - Wesley Cheng <quic_wcheng@quicinc.com> 13 Qualcomm High-Speed USB PHY 18 - items: 19 - enum: 20 - qcom,sa8775p-usb-hs-phy [all …]`
H A D	phy-stm32-usbphyc.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics STM32 USB HS PHY controller 11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI 12 switch. It controls PHY configuration and status, and the UTMI+ switch that 13 selects either OTG or HOST controller for the second PHY port. It also sets 19 \|_ PHY port#1 _________________ HOST controller 22 \|_ PHY port#2 ----\| \|________________ [all …]
H A D	qcom,usb-hs-phy.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm's USB HS PHY 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 17 - qcom,usb-hs-phy-apq8064 18 - qcom,usb-hs-phy-msm8660 19 - qcom,usb-hs-phy-msm8960 25 reset-names: [all …]`
H A D	brcm,stingray-usb-phy.txt	1 Broadcom Stingray USB PHY 4 - compatible : should be one of the listed compatibles 5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS. 6 - "brcm,sr-usb-hs-phy" is a single HS PHY. 7 - reg: offset and length of the PHY blocks registers 8 - #phy-cells: 9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate 10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY. 11 - Must be 0 for brcm,sr-usb-hs-phy. 13 Refer to phy/phy-bindings.txt for the generic PHY binding properties [all …]
H A D	qcom,usb-hs-phy.txt	`1 Qualcomm's USB HS PHY 5 - compatible: 8 Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the 11 "qcom,usb-hs-phy-apq8064" 12 "qcom,usb-hs-phy-msm8916" 13 "qcom,usb-hs-phy-msm8974" 15 - #phy-cells: 20 - clocks: 22 Value type: <prop-encoded-array> 26 - clock-names: [all …]`
H A D	qcom,ipq806x-usb-phy-hs.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER 10 - Ansuel Smith <ansuelsmth@gmail.com> 13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer 14 controllers used in ipq806x. Each DWC3 PHY controller should have its 19 const: qcom,ipq806x-usb-phy-hs 21 "#phy-cells": [all …]`
H A D	transmit-amplitude.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Common PHY and network PCS transmit amplitude property 10 Binding describing the peak-to-peak transmit amplitude for common PHYs 14 - Marek Behún <kabel@kernel.org> 17 tx-p2p-microvolt: 19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property 20 contains multiple values for various PHY modes, the [all …]
H A D	nvidia,tegra20-usb-phy.txt	1 Tegra SOC USB PHY 3 The device node for Tegra SOC USB PHY: 6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy". 7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain 8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is 10 - reg : Defines the following set of registers, in the order listed: 11 - The PHY's own register set. 13 - The register set of the PHY containing the UTMI pad control registers. 14 Present if-and-only-if phy_type == utmi. 15 - phy_type : Should be one of "utmi", "ulpi" or "hsic". [all …]
H A D	qcom-usb-ipq4019-phy.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcom IPQ40xx Dakota HS/SS USB PHY 10 - Robert Marko <robert.marko@sartura.hr> 15 - qcom,usb-ss-ipq4019-phy 16 - qcom,usb-hs-ipq4019-phy 24 reset-names: 26 - const: por_rst [all …]`
H A D	qcom,usb-hs-28nm.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY 10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org> 13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY 18 - qcom,usb-hs-28nm-femtophy 23 "#phy-cells": 28 - description: rpmcc ref clock [all …]`
H A D	nvidia,tegra20-usb-phy.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra USB PHY 10 - Dmitry Osipenko <digetx@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Thierry Reding <thierry.reding@gmail.com> 17 - items: 18 - enum: [all …]`
H A D	fsl,imx8mq-usb-phy.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Freescale i.MX8MQ USB3 PHY 10 - Li Jun <jun.li@nxp.com> 15 - fsl,imx8mq-usb-phy 16 - fsl,imx8mp-usb-phy 21 "#phy-cells": 27 clock-names: [all …]`
H A D	renesas,rcar-gen2-usb-phy.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas R-Car Gen2 USB PHY 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 15 - enum: 16 - renesas,usb-phy-r8a7742 # RZ/G1H 17 - renesas,usb-phy-r8a7743 # RZ/G1M 18 - renesas,usb-phy-r8a7744 # RZ/G1N [all …]`
H A D	socionext,uniphier-usb3hs-phy.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Socionext UniPhier USB3 High-Speed (HS) PHY 10 This describes the devicetree bindings for PHY interfaces built into 12 Although the controller includes High-Speed PHY and Super-Speed PHY, 13 this describes about High-Speed PHY. 16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 21 - socionext,uniphier-pro5-usb3-hsphy [all …]
H A D	rcar-gen2-phy.txt	1 * Renesas R-Car generation 2 USB PHY 3 This file provides information on what the device node for the R-Car generation 4 2 USB PHY contains. 7 - compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC. 8 "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC. 9 "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC. 10 "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC. 11 "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC. 12 "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC. 13 "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC. [all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A D	stm32mp135f-dhcor-dhsbc.dts	`1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 6 * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG 7 * DHCOR PCB number: 718-100 or newer 8 * DHSBC PCB number: 719-100 or newer 11 /dts-v1/; 13 #include <dt-bindings/regulator/st,stm32mp13-regulator.h> 16 #include "stm32mp13xx-dhcor-som.dtsi" 20 compatible = "dh,stm32mp135f-dhcor-dhsbc", 21 "dh,stm32mp135f-dhcor-som", 32 stdout-path = "serial0:115200n8"; [all …]`
H A D	stm32mp135f-dk.dts	`1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 7 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/leds/common.h> 12 #include <dt-bindings/regulator/st,stm32mp13-regulator.h> 15 #include "stm32mp13-pinctrl.dtsi" 18 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 19 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; [all …]`
H A D	stm32mp157c-ev1.dts	`1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 6 /dts-v1/; 8 #include "stm32mp157c-ed1.dts" 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-binding [all...]`
H A D	stm32mp15xx-dkx.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/mfd/st,stpmic1.h> 22 reserved-memory { 23 #address-cell [all...]`
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A D	mediatek,mtk-xhci.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 14 - $ref: usb-xhci.yaml 19 case 2: supports dual-role mode, and the host is based on xHCI driver. 25 - enum: 26 - mediatek,mt2701-xhci 27 - mediatek,mt2712-xhci [all …]`
H A D	snps,dwc3.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Felipe Balbi <balbi@kernel.org> 14 be presented as a standalone DT node with an optional vendor-specific 18 - $ref: usb-drd.yaml# 19 - if: 25 - dr_mode 29 $ref: usb-xhci.yaml# 35 - const: snps,dwc3 [all …]`
H A D	mediatek,mtu3.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 14 - $ref: usb-drd.yaml 23 - enum: 24 - mediatek,mt2712-mtu3 25 - mediatek,mt8173-mtu3 26 - mediatek,mt8183-mtu3 27 - mediatek,mt8186-mtu3 [all …]`
/freebsd/sys/contrib/device-tree/Bindings/media/
H A D	imx7-mipi-csi2.txt	5 -------------- 7 This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is 8 compatible with previous version of Samsung D-phy. 12 - compatible : "fsl,imx7-mipi-csi2"; 13 - reg : base address and length of the register set for the device; 14 - interrupts : should contain MIPI CSIS interrupt; 15 - clocks : list of clock specifiers, see 16 Documentation/devicetree/bindings/clock/clock-bindings.txt for details; 17 - clock-names : must contain "pclk", "wrap" and "phy" entries, matching 19 - power-domains : a phandle to the power domain, see [all …]
/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A D	mediatek,dsi.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 11 - Philipp Zabel <p.zabel@pengutronix.de> 12 - Jitao Shi <jitao.shi@mediatek.com> 16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- 20 - $ref: /schemas/display/dsi-controller.yaml# 25 - enum: 26 - mediatek,mt2701-dsi [all …]`
H A D	mediatek,dsi.txt	5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- 9 - compatible: "mediatek,<chip>-dsi" 10 - the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. 11 - reg: Physical base address and length of the controller's registers 12 - interrupts: The interrupt signal from the function block. 13 - clocks: device clocks 14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 15 - clock-names: must contain "engine", "digital", and "hs" 16 - phys: phandle link to the MIPI D-PHY controller. 17 - phy-names: must contain "dphy" [all …]

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