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1 RISC-V Hart-Level Interrupt Controller (HLIC)7 Every interrupt is ultimately routed through a hart's HLIC before it11 attached to every HLIC: software interrupts, the timer interrupt, and external15 interrupts connect all other device interrupts to the HLIC, which are routed19 required to have a HLIC with these three interrupt sources present. Since the20 interrupt map is defined by the ISA it's not listed in the HLIC's device tree42 An example device tree entry for a HLIC is show below.
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)13 to the core. Every interrupt is ultimately routed through a hart's HLIC17 attached to every HLIC namely software interrupts, the timer interrupt, and22 the HLIC, which are routed via the platform-level interrupt controller26 required to have a HLIC with these three interrupt sources present. Since27 the interrupt map is defined by the ISA it's not listed in the HLIC's device