Searched full:harts (Results 1 – 17 of 17) sorted by relevance
80 * sbi_shutdown() - Remove all the harts from executing supervisor code.324 * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.325 * @cpu_mask: A cpu mask containing all the target harts.338 * remote harts for a virtual address range belonging to a specific ASID or not.340 * @cpu_mask: A cpu mask containing all the target harts.364 * harts for the specified guest physical address range.365 * @cpu_mask: A cpu mask containing all the target harts.382 * remote harts for a guest physical address range belonging to a specific VMID.384 * @cpu_mask: A cpu mask containing all the target harts.403 * harts for the current guest virtual address range.[all …]
343 * denominator of extensions supported across all harts. A true list of in c_show()367 * additional extensions not present across all harts. in c_show()
175 * - have too many harts on CONFIG_RISCV_BOOT_SPINWAIT
876 * All "okay" harts should have same isa. Set HWCAP based on in riscv_fill_hwcap_from_ext_list()1003 pr_warn("Zicboz disabled as it is unavailable on some harts\n"); in riscv_user_isa_enable()
37 * informs the remote harts they need to flush their local instruction caches.40 * IPIs for harts that are not currently executing a MM context and instead60 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm()121 pr_warn("%s mismatched between harts %lu and %lu\n", in cbo_get_block_size()169 * concurrently on different harts. in set_icache_stale_mask()223 * across harts will not occur.
107 pr_warn("CBOM size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()114 pr_warn("CBOZ size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()121 pr_warn("CBOP size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()
68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart69 wins a lottery and executes the early boot code while the other harts are73 initialization phase and then will start all other harts using the SBI HSM
49 RISC-V ISA extensions recognized by the kernel and implemented on all harts. The52 be present on all harts in the system.
46 RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc114 // Example 1 (APLIC domains directly injecting interrupt to HARTs):
31 present HARTs in the system.
152 ksft_exit_fail_msg("Zicboz is only present on a subset of harts.\n" in check_no_zicboz_cpus()153 "Use taskset to select a set of harts where Zicboz\n" in check_no_zicboz_cpus()
81 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm_range()
49 /* Global configuration common for all HARTs */
80 * It is guaranteed that all the timers across all the harts are synchronized
633 * run on other HARTs in kvm_riscv_aia_disable()
90 * RISC-V doesn't have heterogeneous harts yet. This need to be part of91 * per_cpu in case of harts with different pmu counters
55 On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific