Searched full:harts (Results 1 – 16 of 16) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | andestech,plmt0.yaml | 11 functionality for a set of HARTs on a RISC-V platform. It has a single
33 Specifies which harts are connected to the PLMT0. Each item must points
35 PLMT0 supports 1 hart up to 32 harts.
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| H A D | sifive,clint.yaml | 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | riscv,imsics.yaml | 22 which is same for given privilege level across CPUs (or HARTs).
26 IMSIC interrupt files at that privilege level across CPUs (or HARTs).
73 This property represents the set of CPUs (or HARTs) for which given
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| H A D | riscv,aplic.yaml | 46 RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
122 // Example 1 (APLIC domains directly injecting interrupt to HARTs):
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| H A D | andestech,plicsw.yaml | 35 Specifies which harts are connected to the PLIC_SW. Each item must points
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| H A D | riscv,cpu-intc.txt | 23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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| H A D | riscv,cpu-intc.yaml | 31 present HARTs in the system.
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| H A D | thead,c900-aclint-sswi.yaml | 14 supervisor-level IPI functionality for a set of HARTs on a supported
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| H A D | sifive,plic-1.0.0.txt | 10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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| H A D | sifive,plic-1.0.0.yaml | 18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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| /freebsd/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | cpus.yaml | 24 having four harts.
116 thead systems where the vector register length is not identical on all harts, or
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| /freebsd/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | riscv,iommu.yaml | 63 RISC-V HARTS. The cause to interrupt vector is software defined
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| /freebsd/sys/riscv/riscv/ |
| H A D | mp_machdep.c | 354 KASSERT(hart < MAXCPU, ("Too many harts.")); in cpu_init_fdt()
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| H A D | pmap.c | 3371 * Sync the i-cache on all harts before updating the PTE in pmap_enter()
3793 * Sync the i-cache on all harts before updating the PTE in pmap_enter_quick_locked()
5162 * RISC-V harts, the writing hart has to execute a data FENCE in pmap_sync_icache()
5163 * before requesting that all remote RISC-V harts execute a in pmap_sync_icache()
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| /freebsd/sys/contrib/device-tree/Bindings/cpu/ |
| H A D | idle-states.yaml | 55 On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
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| /freebsd/contrib/one-true-awk/testdir/ |
| H A D | bib | 8868 Ten fat oxen, and twenty oxen out of the pastures, and an hundred sheep, beside harts, and roebucks…
20317 And from the daughter of Zion all her beauty is departed: her princes are become like harts that fi…
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