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Searched full:harts (Results 1 – 12 of 12) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,imsics.yaml22 which is same for given privilege level across CPUs (or HARTs).
26 IMSIC interrupt files at that privilege level across CPUs (or HARTs).
73 This property represents the set of CPUs (or HARTs) for which given
H A Driscv,aplic.yaml46 RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
114 // Example 1 (APLIC domains directly injecting interrupt to HARTs):
H A Driscv,cpu-intc.txt23 a PLIC interrupt property will typically list the HLICs for all present HARTs
H A Driscv,cpu-intc.yaml31 present HARTs in the system.
H A Dsifive,plic-1.0.0.txt10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
H A Dsifive,plic-1.0.0.yaml18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dsifive,clint.yaml17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml24 having four harts.
/freebsd/sys/riscv/riscv/
H A Dmp_machdep.c354 KASSERT(hart < MAXCPU, ("Too many harts.")); in cpu_init_fdt()
H A Dpmap.c3351 * Sync the i-cache on all harts before updating the PTE in pmap_enter()
3771 * Sync the i-cache on all harts before updating the PTE in pmap_enter_quick_locked()
5138 * RISC-V harts, the writing hart has to execute a data FENCE in pmap_sync_icache()
5139 * before requesting that all remote RISC-V harts execute a in pmap_sync_icache()
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Didle-states.yaml55 On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
/freebsd/contrib/one-true-awk/testdir/
H A Dbib8868 Ten fat oxen, and twenty oxen out of the pastures, and an hundred sheep, beside harts, and roebucks…
20317 And from the daughter of Zion all her beauty is departed: her princes are become like harts that fi…