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/linux/tools/perf/pmu-events/arch/riscv/
H A Driscv-sbi-firmware.json39 "PublicDescription": "Sent IPI to other HART event",
42 "BriefDescription": "Sent IPI to other HART event"
45 "PublicDescription": "Received IPI from other HART event",
48 "BriefDescription": "Received IPI from other HART event"
51 "PublicDescription": "Sent FENCE.I request to other HART event",
54 "BriefDescription": "Sent FENCE.I request to other HART event"
57 "PublicDescription": "Received FENCE.I request from other HART event",
60 "BriefDescription": "Received FENCE.I request from other HART event"
63 "PublicDescription": "Sent SFENCE.VMA request to other HART event",
66 "BriefDescription": "Sent SFENCE.VMA request to other HART event"
[all …]
/linux/arch/riscv/kernel/
H A Dcpu.c27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
30 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
34 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
35 if (*hart == ~0UL) { in riscv_of_processor_hartid()
36 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
40 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
50 int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_early_of_processor_hartid() argument
59 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_early_of_processor_hartid()
60 if (*hart == ~0UL) { in riscv_early_of_processor_hartid()
[all …]
H A Dsmpboot.c75 unsigned long hart; in acpi_parse_rintc() local
92 hart = processor->hart_id; in acpi_parse_rintc()
93 if (hart == INVALID_HARTID) { in acpi_parse_rintc()
98 if (hart == cpuid_to_hartid_map(0)) { in acpi_parse_rintc()
109 cpuid_to_hartid_map(cpu_count) = hart; in acpi_parse_rintc()
126 unsigned long hart; in of_parse_and_init_cpus() local
132 rc = riscv_early_of_processor_hartid(dn, &hart); in of_parse_and_init_cpus()
136 if (hart == cpuid_to_hartid_map(0)) { in of_parse_and_init_cpus()
144 cpuid, hart); in of_parse_and_init_cpus()
148 cpuid_to_hartid_map(cpuid) = hart; in of_parse_and_init_cpus()
[all …]
H A Dmachine_kexec.c110 * No more interrupts on this hart in machine_shutdown()
149 * suspended and this hart will be the new boot hart.
173 pr_notice("Will call new kernel at %08lx from hart id %lx\n", in machine_kexec()
177 /* Make sure the relocation code is visible to the hart */ in machine_kexec()
H A Dhead.S187 * Park this hart if we:
265 /* Pick one hart to run the main boot sequence */
343 * This hart didn't win the lottery, so we wait for the winning hart to
/linux/Documentation/devicetree/bindings/iio/addac/
H A Dadi,ad74115.yaml70 10 - Current output with HART
71 11 - Current input, externally-powered, with HART
72 12 - Current input, loop-powered, with HART
188 adi,dac-hart-slew:
190 description: Whether to use a HART-compatible slew rate.
268 3 - Control HART CD
269 4 - Monitor HART CD
270 5 - Monitor HART EOM status
282 3 - Control HART RXD
283 4 - Monitor HART RXD
[all …]
H A Dadi,ad74413r.yaml20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
81 HART functions are not supported on AD74412R.
/linux/arch/riscv/mm/
H A Dcacheflush.c30 * the IPI. The RISC-V spec states that a hart must execute a data fence in flush_icache_all()
52 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
55 * execution resumes on each hart.
64 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
67 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
81 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm()
82 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
84 * messages are sent we still need to order this hart's writes in flush_icache_mm()
187 * Mark every other hart's icache as needing a flush for in set_icache_stale_mask()
231 * process is migrated, the corresponding hart's icache will be guaranteed to be
[all …]
H A Dcontext.c241 * we polluted the TLB of current HART so let's do TLB flushed in asids_init()
289 * behavior in a common case (a bunch of single-hart processes on a many-hart
292 * cache flush to be performed before execution resumes on each hart. This
294 * refers to the current hart.
304 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-icicle-kit-fabric.dtsi33 interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
43 interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
/linux/arch/riscv/include/asm/
H A Dcpu_ops_sbi.h16 * struct sbi_hart_boot_data - Hart specific boot used during booting and
18 * @task_ptr: A pointer to the hart specific tp
19 * @stack_ptr: A pointer to the hart specific sp
H A Dsmp.h57 /* Secondary hart entry */
61 * Obtains the hart ID of the currently executing task. This relies on
H A Dbarrier.h46 * task is marked as available for scheduling on a new hart. While I don't see
50 * the new hart.
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
/linux/arch/csky/abiv2/
H A Dcacheflush.c47 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
71 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm_range()
75 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
/linux/Documentation/arch/riscv/
H A Dcmodx.rst47 migrate a task onto a new hart. If migration occurs after the userspace
49 new hart will no longer be clean. This is due to the behavior of fence.i only
50 affecting the hart that it is called on. Thus, the hart that the task has been
61 when the memory map being used by a hart changes. If the prctl() context caused
H A Duabi.rst47 "isa" and "hart isa" lines in /proc/cpuinfo
52 "hart isa" line, in contrast, describes the set of extensions recognized by the
53 kernel on the particular hart being described, even if those extensions may not
/linux/drivers/mailbox/
H A Dmailbox-mchp-ipc-sbi.c180 /* Find out the hart that originated the irq */ in mchp_ipc_cluster_aggr_isr()
206 * the status of the message present and message clear interrupts for each cluster/hart in mchp_ipc_cluster_aggr_isr()
207 * (from hart 0 to hart 5). Each cluster can have up to 5 fixed channels associated. in mchp_ipc_cluster_aggr_isr()
211 /* Find out the destination hart that triggered the interrupt */ in mchp_ipc_cluster_aggr_isr()
216 * the target hart has a greater index than our own in mchp_ipc_cluster_aggr_isr()
222 * Calculate the channel id given the hart and channel index. Channel IDs in mchp_ipc_cluster_aggr_isr()
380 irq_name = devm_kasprintf(ipc->dev, GFP_KERNEL, "hart-%lu", hartid); in mchp_ipc_get_cluster_aggr_irq()
/linux/tools/testing/selftests/futex/
H A Drun.sh13 # Darren Hart <dvhart@linux.intel.com>
16 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
/linux/Documentation/devicetree/bindings/timer/
H A Dandestech,plmt0.yaml13 register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
35 PLMT0 supports 1 hart up to 32 harts.
/linux/tools/testing/selftests/futex/functional/
H A Drun.sh12 # Darren Hart <dvhart@linux.intel.com>
15 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
H A Dfutex_requeue_pi_mismatched_ops.c12 * Darren Hart <dvhart@linux.intel.com>
15 * 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
/linux/tools/arch/riscv/include/uapi/asm/
H A Dunistd.h29 * kernel might schedule a process on another hart. There is no way for
31 * thread->hart mappings), so we've defined a RISC-V specific system call to
/linux/drivers/irqchip/
H A Dirq-riscv-aplic-msi.c103 /* Compute target HART Base PPN */ in aplic_msi_write_msg()
110 /* Compute target group and hart indexes */ in aplic_msi_write_msg()
212 /* Find number of HART index bits (LHXW) */ in aplic_msi_setup()
215 dev_err(dev, "IMSIC hart index bits big for APLIC LHXW\n"); in aplic_msi_setup()
/linux/tools/testing/selftests/futex/include/
H A Datomic.h11 * Darren Hart <dvhart@linux.intel.com>
14 * 2009-Nov-17: Initial version by Darren Hart <dvhart@linux.intel.com>

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