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/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dmicrochip,sbi-ipc.yaml23 Inter-hart Communication (IHC) IP.
43 - hart-0
44 - hart-1
45 - hart-2
46 - hart-3
47 - hart-4
48 - hart-5
111 interrupt-names = "hart-1", "hart-2", "hart-3";
121 interrupt-names = "hart-1", "hart-2", "hart-3";
/freebsd/sys/contrib/device-tree/Bindings/iio/addac/
H A Dadi,ad74115.yaml70 10 - Current output with HART
71 11 - Current input, externally-powered, with HART
72 12 - Current input, loop-powered, with HART
188 adi,dac-hart-slew:
190 description: Whether to use a HART-compatible slew rate.
268 3 - Control HART CD
269 4 - Monitor HART CD
270 5 - Monitor HART EOM status
282 3 - Control HART RXD
283 4 - Monitor HART RX
[all...]
H A Dadi,ad74413r.yaml20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
81 HART functions are not supported on AD74412R.
/freebsd/sys/riscv/riscv/
H A Dmp_machdep.c151 init_secondary(uint64_t hart) in init_secondary() argument
157 cpuid = hart; in init_secondary()
166 /* Workaround: make sure wfi doesn't halt the hart */ in init_secondary()
188 /* Activate this hart in the kernel pmap. */ in init_secondary()
189 CPU_SET_ATOMIC(hart, &kernel_pmap->pm_active); in init_secondary()
318 /* Check if this hart supports MMU. */ in cpu_check_mmu()
331 uint64_t hart; in cpu_init_fdt() local
348 hart = reg[0]; in cpu_init_fdt()
350 hart <<= 32; in cpu_init_fdt()
351 hart |= reg[1]; in cpu_init_fdt()
[all …]
H A Dplic.c135 int hart; in plic_get_hartid() local
138 if (OF_searchencprop(intc, "#interrupt-cells", &hart, in plic_get_hartid()
139 sizeof(hart)) == -1) { in plic_get_hartid()
147 * interested in, so search for its hart ID. in plic_get_hartid()
149 if (OF_searchencprop(OF_parent(intc), "reg", (pcell_t *)&hart, in plic_get_hartid()
150 sizeof(hart)) == -1) { in plic_get_hartid()
155 return (hart); in plic_get_hartid()
305 int hart; in plic_attach() local
367 * its hart ID. in plic_attach()
369 * 3. Convert the hart to a cpuid, and calculate the register offsets in plic_attach()
[all …]
H A Didentcpu.c373 u_int hart; in identify_cpu_features_fdt() local
381 hart = pcpu_find(cpu)->pc_hart; in identify_cpu_features_fdt()
394 reg != hart) in identify_cpu_features_fdt()
401 "for CPU %d, hart %u\n", __func__, cpu, hart); in identify_cpu_features_fdt()
424 printf("%s: could not find FDT node for CPU %u, hart %u\n", in identify_cpu_features_fdt()
425 __func__, cpu, hart); in identify_cpu_features_fdt()
568 u_int hart; in printcpuinfo() local
571 hart = pcpu_find(cpu)->pc_hart; in printcpuinfo()
585 printf("CPU %-3u: Vendor=%s Core=%s (Hart %u)\n", cpu, in printcpuinfo()
586 desc->cpu_mvendor_name, desc->cpu_march_name, hart); in printcpuinfo()
H A Dmachdep.c117 uint32_t boot_hart = BOOT_HART_INVALID; /* The hart we booted on. */
425 uint32_t hart; in parse_boot_hartid() local
439 * Look for the boot hart ID. This was either passed in directly from in parse_boot_hartid()
444 if (OF_getencprop(chosen, "boot-hartid", &hart, sizeof(hart)) != -1) { in parse_boot_hartid()
445 boot_hart = hart; in parse_boot_hartid()
451 panic("Boot hart ID was not properly set"); in parse_boot_hartid()
455 PCPU_SET(hart, boot_hart); in parse_boot_hartid()
H A Dsbi.c161 printf("SBI: PolarFire Hart Software Services %lu\n", in sbi_print_version()
263 sbi_hsm_hart_start(u_long hart, u_long start_addr, u_long priv) in sbi_hsm_hart_start() argument
267 ret = SBI_CALL3(SBI_EXT_ID_HSM, SBI_HSM_HART_START, hart, start_addr, in sbi_hsm_hart_start()
279 sbi_hsm_hart_status(u_long hart) in sbi_hsm_hart_status() argument
283 ret = SBI_CALL1(SBI_EXT_ID_HSM, SBI_HSM_HART_STATUS, hart); in sbi_hsm_hart_status()
H A Daplic.c198 * interested in, so search for its hart ID. in fdt_get_hartid()
386 /* Get the hart ID from the CLIC's phandle. */ in aplic_setup_direct_mode()
396 device_printf(dev, "Invalid cpu for hart %d\n", hartid); in aplic_setup_direct_mode()
455 /* APLIC with IMSIC on hart is not supported */ in aplic_attach()
527 device_printf(dev, "Bind irq %d to cpu%d (hart %d)\n", src->irq, in aplic_bind_intr()
H A Dlocore.S58 * - a0 = hart ID
61 * Multiple CPUs might enter from this point, so we perform a hart lottery and
72 /* Pick a hart to run the boot process. */
84 /* Store the boot hart */
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dthead,c900-aclint-sswi.yaml16 HART connected to the SSWI device. See draft specification
46 riscv,hart-indexes:
51 A list of hart indexes that APLIC should use to address each hart
71 - riscv,hart-indexes
74 riscv,hart-indexes: false
101 riscv,hart-indexes = <0x0 0x1 0x10 0x11>;
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
H A Driscv,imsics.yaml17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
33 privilege level (machine or supervisor) encodes group index, HART index,
36 XLEN-1 > (HART Index MSB) 12 0
39 |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
76 HART) as parent.
101 riscv,hart-index-bits:
105 Number of HART index bits in the MSI target address. When not
H A Driscv,cpu-intc.yaml7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
H A Dsifive,plic-1.0.0.txt7 hart contexts in the system, via the external interrupt source in each hart.
9 A hart context is a privilege mode in a hardware execution thread. For example,
11 privilege modes per hart; machine mode and supervisor mode.
H A Driscv,aplic.yaml47 node, which has a CPU node (i.e. RISC-V HART) as parent.
94 riscv,hart-indexes:
99 A list of hart indexes that APLIC should use to address each hart
H A Dsifive,plic-1.0.0.yaml14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
17 A hart context is a privilege mode in a hardware execution thread. For example,
19 privilege modes per hart; machine mode and supervisor mode.
/freebsd/sys/riscv/include/
H A Dsbi.h96 /* Hart State Management (HSM) Extension */
189 /* Hart State Management extension functions. */
192 * Start execution on the specified hart at physical address start_addr. The
193 * register a0 will contain the hart's ID, and a1 will contain the value of
196 int sbi_hsm_hart_start(u_long hart, u_long start_addr, u_long priv);
199 * Stop execution on the current hart. Interrupts should be disabled, or this
205 * Get the execution status of the specified hart. The status will be one of:
211 int sbi_hsm_hart_status(u_long hart);
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml18 hart: A hardware execution context, which contains all the state
76 Identifies that the hart uses the RISC-V instruction set
77 and identifies the type of the hart.
82 this hart. These values originate from the RISC-V Privileged
95 The hart ID of this CPU node.
135 by this hart (see ./idle-states.yaml).
211 // Example 2: Spike ISA Simulator with 1 Hart
H A Dextensions.yaml18 This document defines properties that indicate whether a hart supports a
37 supported by the hart. These are documented in the RISC-V
56 The base ISA implemented by this hart, as described by the 20191213
65 description: Extensions supported by the hart.
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dandestech,plmt0.yaml13 register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
35 PLMT0 supports 1 hart up to 32 harts.
/freebsd/contrib/ntp/sntp/
H A DCOPYRIGHT32 Hart, Danny Mayer, Martin Burnicki, and possibly others is:
97 21. [22]Dave Hart <davehart@gmail.com> General maintenance, IPv6
132 Hart-Davis <d@hd.org> ARCRON MSF clock driver
/freebsd/contrib/ntp/
H A DCOPYRIGHT32 Hart, Danny Mayer, Martin Burnicki, and possibly others is:
97 21. [22]Dave Hart <davehart@gmail.com> General maintenance, IPv6
132 Hart-Davis <d@hd.org> ARCRON MSF clock driver
H A DNEWS24 stepped. <hart@ntp.org>
26 <hart@ntp.org>
28 * [Bug 3910] Memory leak using openssl-3 <hart@ntp.org>
30 <hart@ntp.org>
32 <hart@ntp.org>
33 * [Bug 3901] LIB_GETBUF isn't thread-safe. <hart@ntp.org>
35 Windows. <hart@ntp.org>
37 duplicate associations. <hart@ntp.org>
38 * [Bug 3872] Ignore restrict mask for hostname. <hart@ntp.org>
41 declaration from ntp_types.h to config.h. <hart
[all...]
/freebsd/usr.sbin/bhyve/riscv/
H A Dbhyverun_machdep.c192 /* Set hart ID. */ in bhyve_start_vcpu()
336 /* Set FDT base address to the bootable hart. */ in bhyve_init_platform()

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