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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dallwinner,sun4i-a10-gates-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
7 title: Allwinner A10 Bus Gates Clock
24 - const: allwinner,sun4i-a10-gates-clk
25 - const: allwinner,sun4i-a10-axi-gates-clk
26 - const: allwinner,sun4i-a10-ahb-gates-clk
27 - const: allwinner,sun5i-a10s-ahb-gates-clk
28 - const: allwinner,sun5i-a13-ahb-gates-clk
29 - const: allwinner,sun7i-a20-ahb-gates-clk
30 - const: allwinner,sun6i-a31-ahb1-gates-clk
31 - const: allwinner,sun8i-a23-ahb1-gates-clk
[all …]
H A Dallwinner,sun8i-h3-bus-gates-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml#
7 title: Allwinner A10 Bus Gates Clock
23 const: allwinner,sun8i-h3-bus-gates-clk
59 compatible = "allwinner,sun8i-h3-bus-gates-clk";
H A Drenesas,cpg-mstp-clocks.yaml13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
14 organized in groups of up to 32 gates.
H A Dst,nomadik.txt7 PLLs and clock gates.
34 HCLK nodes: these represent the clock gates on individual
/freebsd/sys/dev/clk/rockchip/
H A Drk_cru.c186 if (sc->gates[i].name == NULL) in rk_cru_register_gates()
189 def.clkdef.id = sc->gates[i].id; in rk_cru_register_gates()
190 def.clkdef.name = sc->gates[i].name; in rk_cru_register_gates()
191 def.clkdef.parent_names = &sc->gates[i].parent_name; in rk_cru_register_gates()
193 def.offset = sc->gates[i].offset; in rk_cru_register_gates()
194 def.shift = sc->gates[i].shift; in rk_cru_register_gates()
272 if (sc->gates) in rk_cru_attach()
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Drk3128-cru.h19 /* sclk gates (special clocks) */
70 /* dclk gates */
74 /* aclk gates */
90 /* pclk gates */
121 /* hclk gates */
H A Drk3228-cru.h17 /* sclk gates (special clocks) */
69 /* dclk gates */
73 /* aclk gates */
92 /* pclk gates */
119 /* hclk gates */
H A Drk3036-cru.h16 /* sclk gates (special clocks) */
51 /* aclk gates */
59 /* pclk gates */
80 /* hclk gates */
H A Drk3328-cru.h18 /* sclk gates (special clocks) */
93 /* dclk gates */
100 /* aclk gates */
130 /* pclk gates */
169 /* hclk gates */
H A Dpx30-cru.h15 /* sclk gates (special clocks) */
91 /* dclk gates */
95 /* aclk gates */
115 /* hclk gates */
142 /* pclk gates */
H A Dsun4i-a10-ccu.h50 /* AHB Gates */
95 /* APB0 Gates */
107 /* APB1 Gates */
162 /* DRAM Gates */
H A Drk3188-cru-common.h19 /* sclk gates (special clocks) */
54 /* aclk gates */
71 /* pclk gates */
107 /* hclk gates */
H A Drv1108-cru.h16 /* sclk gates (special clocks) */
85 /* aclk gates */
106 /* pclk gates */
138 /* hclk gates */
H A Drk3368-cru.h19 /* sclk gates (special clocks) */
86 /* aclk gates */
106 /* pclk gates */
155 /* hclk gates */
H A Drk3288-cru.h18 /* sclk gates (special clocks) */
90 /* aclk gates */
111 /* pclk gates */
165 /* hclk gates */
H A Ds3c2410.h30 /* pclk-gates */
45 /* hclk-gates */
H A Ds3c2412.h40 /* pclk-gates */
55 /* hclk-gates */
H A Ds3c2443.h46 /* hclk-gates */
67 /* pclk-gates */
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-gate.txt2 to the i2c bus. Gates are similar to arbitrators in that you need to perform
4 there are no competing masters to consider for gates and therefore there is
5 no arbitration happening for gates.
H A Di2c-gate.yaml14 to the i2c bus. Gates are similar to arbitrators in that you need to perform
16 there are no competing masters to consider for gates and therefore there is
17 no arbitration happening for gates.
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dallwinner,sun6i-a31-prcm.yaml32 - allwinner,sun6i-a31-apb0-gates-clk
98 const: allwinner,sun6i-a31-apb0-gates-clk
199 apb0_gates: apb0-gates-clk {
200 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
H A Dallwinner,sun8i-a23-prcm.yaml32 - allwinner,sun8i-a23-apb0-gates-clk
75 const: allwinner,sun8i-a23-apb0-gates-clk
150 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
/freebsd/sys/dev/clk/allwinner/
H A Daw_ccung.c187 if (sc->gates[i].name == NULL) in aw_ccung_register_gates()
191 def.clkdef.name = sc->gates[i].name; in aw_ccung_register_gates()
192 def.clkdef.parent_names = &sc->gates[i].parent_name; in aw_ccung_register_gates()
194 def.offset = sc->gates[i].offset; in aw_ccung_register_gates()
195 def.shift = sc->gates[i].shift; in aw_ccung_register_gates()
324 if (sc->gates) in aw_ccung_attach()
/freebsd/contrib/expat/tests/
H A Dmisc_tests.h19 Copyright (c) 2020 Tim Gates <tim.gates@iress.com>
H A Dalloc_tests.h19 Copyright (c) 2020 Tim Gates <tim.gates@iress.com>

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