xref: /freebsd/sys/contrib/device-tree/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0)
1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2021-2022 TQ-Systems GmbH
4 * Author: Alexander Stein <alexander.stein@tq-group.com>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/leds/common.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12#include <dt-bindings/pwm/pwm.h>
13#include "imx8mp-tqma8mpql.dtsi"
14
15/ {
16	model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
17	compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
18	chassis-type = "embedded";
19
20	chosen {
21		stdout-path = &uart4;
22	};
23
24	iio-hwmon {
25		compatible = "iio-hwmon";
26		io-channels = <&adc 0>, <&adc 1>;
27	};
28
29	aliases {
30		mmc0 = &usdhc3;
31		mmc1 = &usdhc2;
32		mmc2 = &usdhc1;
33		rtc0 = &pcf85063;
34		rtc1 = &snvs_rtc;
35		spi0 = &flexspi;
36		spi1 = &ecspi1;
37		spi2 = &ecspi2;
38		spi3 = &ecspi3;
39	};
40
41	backlight_lvds: backlight {
42		compatible = "pwm-backlight";
43		pinctrl-names = "default";
44		pinctrl-0 = <&pinctrl_backlight>;
45		pwms = <&pwm2 0 5000000 0>;
46		brightness-levels = <0 4 8 16 32 64 128 255>;
47		default-brightness-level = <7>;
48		power-supply = <&reg_vcc_12v0>;
49		enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
50		status = "disabled";
51	};
52
53	clk_xtal25: clk-xtal25 {
54		compatible = "fixed-clock";
55		#clock-cells = <0>;
56		clock-frequency = <25000000>;
57	};
58
59	connector {
60		compatible = "gpio-usb-b-connector", "usb-b-connector";
61		type = "micro";
62		label = "X29";
63		pinctrl-names = "default";
64		pinctrl-0 = <&pinctrl_usbcon0>;
65		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
66
67		port {
68			usb_dr_connector: endpoint {
69				remote-endpoint = <&usb3_dwc>;
70			};
71		};
72	};
73
74	fan0: pwm-fan {
75		compatible = "pwm-fan";
76		pinctrl-names = "default";
77		pinctrl-0 = <&pinctrl_pwmfan>;
78		fan-supply = <&reg_pwm_fan>;
79		#cooling-cells = <2>;
80		/* typical 25 kHz -> 40.000 nsec */
81		pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>;
82		cooling-levels = <0 32 64 128 196 240>;
83		pulses-per-revolution = <2>;
84		interrupt-parent = <&gpio5>;
85		interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
86		status = "disabled";
87	};
88
89	gpio-keys {
90		compatible = "gpio-keys";
91		pinctrl-names = "default";
92		pinctrl-0 = <&pinctrl_gpiobutton>;
93		autorepeat;
94
95		switch-1 {
96			label = "S12";
97			linux,code = <BTN_0>;
98			gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
99			wakeup-source;
100		};
101
102		switch-2 {
103			label = "S13";
104			linux,code = <BTN_1>;
105			gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
106			wakeup-source;
107		};
108	};
109
110	gpio-leds {
111		compatible = "gpio-leds";
112		pinctrl-names = "default";
113		pinctrl-0 = <&pinctrl_gpioled>;
114
115		led-0 {
116			color = <LED_COLOR_ID_GREEN>;
117			function = LED_FUNCTION_STATUS;
118			function-enumerator = <0>;
119			gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
120			linux,default-trigger = "default-on";
121		};
122
123		led-1 {
124			color = <LED_COLOR_ID_GREEN>;
125			function = LED_FUNCTION_HEARTBEAT;
126			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
127			linux,default-trigger = "heartbeat";
128		};
129
130		led-2 {
131			color = <LED_COLOR_ID_YELLOW>;
132			function = LED_FUNCTION_STATUS;
133			function-enumerator = <1>;
134			gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
135		};
136	};
137
138	display: display {
139		/*
140		 * Display is not fixed, so compatible has to be added from
141		 * DT overlay
142		 */
143		pinctrl-names = "default";
144		pinctrl-0 = <&pinctrl_lvdsdisplay>;
145		power-supply = <&reg_vcc_3v3>;
146		enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
147		backlight = <&backlight_lvds>;
148		status = "disabled";
149	};
150
151	reg_pwm_fan: regulator-pwm-fan {
152		compatible = "regulator-fixed";
153		pinctrl-names = "default";
154		pinctrl-0 = <&pinctrl_regpwmfan>;
155		regulator-name = "FAN_PWR";
156		regulator-min-microvolt = <12000000>;
157		regulator-max-microvolt = <12000000>;
158		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
159		enable-active-high;
160		vin-supply = <&reg_vcc_12v0>;
161	};
162
163	reg_usdhc2_vmmc: regulator-usdhc2 {
164		compatible = "regulator-fixed";
165		pinctrl-names = "default";
166		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
167		regulator-name = "VSD_3V3";
168		regulator-min-microvolt = <3300000>;
169		regulator-max-microvolt = <3300000>;
170		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
171		enable-active-high;
172		startup-delay-us = <100>;
173		off-on-delay-us = <12000>;
174	};
175
176	reg_vcc_12v0: regulator-12v0 {
177		compatible = "regulator-fixed";
178		pinctrl-names = "default";
179		pinctrl-0 = <&pinctrl_reg12v0>;
180		regulator-name = "VCC_12V0";
181		regulator-min-microvolt = <12000000>;
182		regulator-max-microvolt = <12000000>;
183		gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
184		enable-active-high;
185	};
186
187	reg_vcc_1v8: regulator-1v8 {
188		compatible = "regulator-fixed";
189		regulator-name = "VCC_1V8";
190		regulator-min-microvolt = <1800000>;
191		regulator-max-microvolt = <1800000>;
192	};
193
194	reg_vcc_3v3: regulator-3v3 {
195		compatible = "regulator-fixed";
196		regulator-name = "VCC_3V3";
197		regulator-min-microvolt = <3300000>;
198		regulator-max-microvolt = <3300000>;
199	};
200
201	reg_vcc_5v0: regulator-5v0 {
202		compatible = "regulator-fixed";
203		regulator-name = "VCC_5V0";
204		regulator-min-microvolt = <5000000>;
205		regulator-max-microvolt = <5000000>;
206	};
207
208	reserved-memory {
209		#address-cells = <2>;
210		#size-cells = <2>;
211		ranges;
212
213		ocram: ocram@900000 {
214			no-map;
215			reg = <0 0x900000 0 0x70000>;
216		};
217
218		/* global autoconfigured region for contiguous allocations */
219		linux,cma {
220			compatible = "shared-dma-pool";
221			reusable;
222			size = <0 0x38000000>;
223			alloc-ranges = <0 0x40000000 0 0xB0000000>;
224			linux,cma-default;
225		};
226	};
227
228	sound {
229		compatible = "fsl,imx-audio-tlv320aic32x4";
230		model = "tq-tlv320aic32x";
231		audio-cpu = <&sai3>;
232		audio-codec = <&tlv320aic3x04>;
233	};
234
235	thermal-zones {
236		soc-thermal {
237			trips {
238				soc_active0: trip-active0 {
239					temperature = <40000>;
240					hysteresis = <5000>;
241					type = "active";
242				};
243
244				soc_active1: trip-active1 {
245					temperature = <48000>;
246					hysteresis = <3000>;
247					type = "active";
248				};
249
250				soc_active2: trip-active2 {
251					temperature = <60000>;
252					hysteresis = <10000>;
253					type = "active";
254				};
255			};
256
257			cooling-maps {
258				map1 {
259					trip = <&soc_active0>;
260					cooling-device = <&fan0 1 1>;
261				};
262
263				map2 {
264					trip = <&soc_active1>;
265					cooling-device = <&fan0 2 2>;
266				};
267
268				map3 {
269					trip = <&soc_active2>;
270					cooling-device = <&fan0 3 3>;
271				};
272			};
273		};
274	};
275};
276
277&ecspi1 {
278	pinctrl-names = "default";
279	pinctrl-0 = <&pinctrl_ecspi1>;
280	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
281	status = "okay";
282};
283
284&ecspi2 {
285	pinctrl-names = "default";
286	pinctrl-0 = <&pinctrl_ecspi2>;
287	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
288	status = "okay";
289};
290
291&ecspi3 {
292	pinctrl-names = "default";
293	pinctrl-0 = <&pinctrl_ecspi3>;
294	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
295	status = "okay";
296
297	adc: adc@0 {
298		reg = <0>;
299		compatible = "microchip,mcp3202";
300		/* 100 ksps * 18 */
301		spi-max-frequency = <1800000>;
302		vref-supply = <&reg_vcc_3v3>;
303		#io-channel-cells = <1>;
304	};
305};
306
307&eqos {
308	pinctrl-names = "default";
309	pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>;
310	phy-mode = "rgmii-id";
311	phy-handle = <&ethphy3>;
312	status = "okay";
313
314	mdio {
315		compatible = "snps,dwmac-mdio";
316		#address-cells = <1>;
317		#size-cells = <0>;
318
319		ethphy3: ethernet-phy@3 {
320			compatible = "ethernet-phy-ieee802.3-c22";
321			reg = <3>;
322			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
323			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
324			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
325			ti,dp83867-rxctrl-strap-quirk;
326			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
327			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
328			reset-assert-us = <500000>;
329			reset-deassert-us = <50000>;
330			enet-phy-lane-no-swap;
331			interrupt-parent = <&gpio4>;
332			interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
333		};
334	};
335};
336
337&fec {
338	pinctrl-names = "default";
339	pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>;
340	phy-mode = "rgmii-id";
341	phy-handle = <&ethphy0>;
342	fsl,magic-packet;
343	status = "okay";
344
345	mdio {
346		#address-cells = <1>;
347		#size-cells = <0>;
348
349		ethphy0: ethernet-phy@0 {
350			compatible = "ethernet-phy-ieee802.3-c22";
351			reg = <0>;
352			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
353			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
354			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
355			ti,dp83867-rxctrl-strap-quirk;
356			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
357			reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
358			reset-assert-us = <500000>;
359			reset-deassert-us = <50000>;
360			enet-phy-lane-no-swap;
361			interrupt-parent = <&gpio4>;
362			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
363		};
364	};
365};
366
367&flexcan1 {
368	pinctrl-names = "default";
369	pinctrl-0 = <&pinctrl_flexcan1>;
370	xceiver-supply = <&reg_vcc_3v3>;
371	status = "okay";
372};
373
374&flexcan2 {
375	pinctrl-names = "default";
376	pinctrl-0 = <&pinctrl_flexcan2>;
377	xceiver-supply = <&reg_vcc_3v3>;
378	status = "okay";
379};
380
381&gpio1 {
382	pinctrl-names = "default";
383	pinctrl-0 = <&pinctrl_gpio1>;
384
385	gpio-line-names = "GPO1", "GPO0", "", "GPO3",
386			  "", "", "GPO2", "GPI0",
387			  "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#",
388			  "OTG_PWR", "", "GPI2", "GPI3",
389			  "", "", "", "",
390			  "", "", "", "",
391			  "", "", "", "",
392			  "", "", "", "";
393};
394
395&gpio2 {
396	pinctrl-names = "default";
397	pinctrl-0 = <&pinctrl_hoggpio2>;
398
399	gpio-line-names = "", "", "", "",
400			  "", "", "VCC12V_EN", "PERST#",
401			  "", "", "CLKREQ#", "PEWAKE#",
402			  "USDHC2_CD", "", "", "",
403			  "", "", "", "V_SD3V3_EN",
404			  "", "", "", "",
405			  "", "", "", "",
406			  "", "", "", "";
407
408	perst-hog {
409		gpio-hog;
410		gpios = <7 0>;
411		output-high;
412		line-name = "PERST#";
413	};
414
415	clkreq-hog {
416		gpio-hog;
417		gpios = <10 0>;
418		input;
419		line-name = "CLKREQ#";
420	};
421
422	pewake-hog {
423		gpio-hog;
424		gpios = <11 0>;
425		input;
426		line-name = "PEWAKE#";
427	};
428};
429
430&gpio3 {
431	gpio-line-names = "", "", "", "",
432			  "", "", "", "",
433			  "", "", "", "",
434			  "", "", "LVDS0_RESET#", "",
435			  "", "", "", "LVDS0_BLT_EN",
436			  "LVDS0_PWR_EN", "", "", "",
437			  "", "", "", "",
438			  "", "", "", "";
439};
440
441&gpio4 {
442	pinctrl-names = "default";
443	pinctrl-0 = <&pinctrl_gpio4>;
444
445	gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#",
446			  "", "", "", "",
447			  "", "", "", "",
448			  "", "", "", "",
449			  "", "", "DP_IRQ", "DSI_EN",
450			  "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "",
451			  "", "", "", "FAN_PWR",
452			  "RTC_EVENT#", "CODEC_RST#", "", "";
453
454	pcie-refclkreq-hog {
455		gpio-hog;
456		gpios = <22 0>;
457		output-high;
458		line-name = "PCIE_REFCLK_OE#";
459	};
460};
461
462&gpio5 {
463	gpio-line-names = "", "", "", "LED2",
464			  "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC",
465			  "CSI0_TRIGGER", "CSI0_ENABLE", "", "",
466			  "", "ECSPI2_SS0", "", "",
467			  "", "", "", "",
468			  "", "", "", "",
469			  "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B",
470			  "", "", "", "";
471};
472
473&i2c2 {
474	clock-frequency = <384000>;
475	pinctrl-names = "default", "gpio";
476	pinctrl-0 = <&pinctrl_i2c2>;
477	pinctrl-1 = <&pinctrl_i2c2_gpio>;
478	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
479	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
480	status = "okay";
481
482	tlv320aic3x04: audio-codec@18 {
483		compatible = "ti,tlv320aic32x4";
484		pinctrl-names = "default";
485		pinctrl-0 = <&pinctrl_tlv320aic3x04>;
486		reg = <0x18>;
487		clock-names = "mclk";
488		clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
489		reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
490		iov-supply = <&reg_vcc_1v8>;
491		ldoin-supply = <&reg_vcc_3v3>;
492	};
493
494	se97_1c: temperature-sensor@1c {
495		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
496		reg = <0x1c>;
497	};
498
499	at24c02_54: eeprom@54 {
500		compatible = "nxp,se97b", "atmel,24c02";
501		reg = <0x54>;
502		pagesize = <16>;
503		vcc-supply = <&reg_vcc_3v3>;
504	};
505
506	pcieclk: clock-generator@6a {
507		compatible = "renesas,9fgv0241";
508		reg = <0x6a>;
509		clocks = <&clk_xtal25>;
510		#clock-cells = <1>;
511	};
512};
513
514&i2c4 {
515	clock-frequency = <384000>;
516	pinctrl-names = "default", "gpio";
517	pinctrl-0 = <&pinctrl_i2c4>;
518	pinctrl-1 = <&pinctrl_i2c4_gpio>;
519	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
520	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
521	status = "okay";
522};
523
524&i2c6 {
525	clock-frequency = <384000>;
526	pinctrl-names = "default", "gpio";
527	pinctrl-0 = <&pinctrl_i2c6>;
528	pinctrl-1 = <&pinctrl_i2c6_gpio>;
529	scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
530	sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
531	status = "okay";
532};
533
534&pcf85063 {
535	/* RTC_EVENT# is connected on MBa8MPxL */
536	pinctrl-names = "default";
537	pinctrl-0 = <&pinctrl_pcf85063>;
538	interrupt-parent = <&gpio4>;
539	interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
540};
541
542&pcie_phy {
543	fsl,clkreq-unsupported;
544	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
545	clocks = <&pcieclk 0>;
546	clock-names = "ref";
547	status = "okay";
548};
549
550&pcie {
551	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
552		 <&clk IMX8MP_CLK_HSIO_AXI>,
553		 <&clk IMX8MP_CLK_PCIE_ROOT>;
554	clock-names = "pcie", "pcie_bus", "pcie_aux";
555	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
556	assigned-clock-rates = <10000000>;
557	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
558	status = "okay";
559};
560
561&pwm2 {
562	pinctrl-names = "default";
563	pinctrl-0 = <&pinctrl_pwm2>;
564	status = "disabled";
565};
566
567&pwm3 {
568	pinctrl-names = "default";
569	pinctrl-0 = <&pinctrl_pwm3>;
570	status = "okay";
571};
572
573&sai3 {
574	pinctrl-names = "default";
575	pinctrl-0 = <&pinctrl_sai3>;
576	assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
577	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
578	assigned-clock-rates = <12288000>;
579	fsl,sai-mclk-direction-output;
580	status = "okay";
581};
582
583&snvs_pwrkey {
584	status = "okay";
585};
586
587&uart1 {
588	pinctrl-names = "default";
589	pinctrl-0 = <&pinctrl_uart1>;
590	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
591	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
592	status = "okay";
593};
594
595&uart2 {
596	pinctrl-names = "default";
597	pinctrl-0 = <&pinctrl_uart2>;
598	assigned-clocks = <&clk IMX8MP_CLK_UART2>;
599	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
600	status = "okay";
601};
602
603&uart3 {
604	pinctrl-names = "default";
605	pinctrl-0 = <&pinctrl_uart3>;
606	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
607	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
608	status = "okay";
609};
610
611&uart4 {
612	/* console */
613	pinctrl-names = "default";
614	pinctrl-0 = <&pinctrl_uart4>;
615	status = "okay";
616};
617
618&usb3_0 {
619	pinctrl-names = "default";
620	pinctrl-0 = <&pinctrl_usb0>;
621	fsl,over-current-active-low;
622	status = "okay";
623};
624
625&usb3_1 {
626	fsl,disable-port-power-control;
627	fsl,permanently-attached;
628	status = "okay";
629};
630
631&usb3_phy0 {
632	vbus-supply = <&reg_vcc_5v0>;
633	status = "okay";
634};
635
636&usb3_phy1 {
637	vbus-supply = <&reg_vcc_5v0>;
638	status = "okay";
639};
640
641&usb_dwc3_0 {
642	/* dual role is implemented, but not a full featured OTG */
643	hnp-disable;
644	srp-disable;
645	adp-disable;
646	dr_mode = "otg";
647	usb-role-switch;
648	role-switch-default-mode = "peripheral";
649	status = "okay";
650
651	port {
652		usb3_dwc: endpoint {
653			remote-endpoint = <&usb_dr_connector>;
654		};
655	};
656};
657
658&usb_dwc3_1 {
659	dr_mode = "host";
660	#address-cells = <1>;
661	#size-cells = <0>;
662	pinctrl-names = "default";
663	pinctrl-0 = <&pinctrl_usbhub>;
664	status = "okay";
665
666	hub_2_0: hub@1 {
667		compatible = "usb451,8142";
668		reg = <1>;
669		peer-hub = <&hub_3_0>;
670		reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
671		vdd-supply = <&reg_vcc_3v3>;
672	};
673
674	hub_3_0: hub@2 {
675		compatible = "usb451,8140";
676		reg = <2>;
677		peer-hub = <&hub_2_0>;
678		reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
679		vdd-supply = <&reg_vcc_3v3>;
680	};
681};
682
683&usdhc2 {
684	pinctrl-names = "default", "state_100mhz", "state_200mhz";
685	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
686	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
687	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
688	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
689	vmmc-supply = <&reg_usdhc2_vmmc>;
690	no-mmc;
691	no-sdio;
692	disable-wp;
693	bus-width = <4>;
694	status = "okay";
695};
696
697&iomuxc {
698	pinctrl_backlight: backlightgrp {
699		fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x14>;
700	};
701
702	pinctrl_flexcan1: flexcan1grp {
703		fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX		0x150>,
704			   <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX		0x150>;
705	};
706
707	pinctrl_flexcan2: flexcan2grp {
708		fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x150>,
709			   <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x150>;
710	};
711
712	/* only on X57, primary used as CSI0 control signals */
713	pinctrl_ecspi1: ecspi1grp {
714		fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO	0x1c0>,
715			   <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI	0x1c0>,
716			   <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK	0x1c0>,
717			   <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x1c0>;
718	};
719
720	/* on X63 and optionally on X57, can also be used as CSI1 control signals */
721	pinctrl_ecspi2: ecspi2grp {
722		fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x1c0>,
723			   <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x1c0>,
724			   <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x1c0>,
725			   <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x1c0>;
726	};
727
728	pinctrl_ecspi3: ecspi3grp {
729		fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI		0x1c0>,
730			   <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK		0x1c0>,
731			   <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO		0x1c0>,
732			   <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25		0x1c0>;
733	};
734
735	pinctrl_eqos: eqosgrp {
736		fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x40000044>,
737			   <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x40000044>,
738			   <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90>,
739			   <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90>,
740			   <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90>,
741			   <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90>,
742			   <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90>,
743			   <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90>,
744			   <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x12>,
745			   <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x12>,
746			   <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x12>,
747			   <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x12>,
748			   <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x12>,
749			   <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x14>;
750	};
751
752	pinctrl_eqos_event: eqosevtgrp {
753		fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT		0x100>,
754			   <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN		0x1c0>;
755	};
756
757	pinctrl_eqos_phy: eqosphygrp {
758		fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02				0x100>,
759			   <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03				0x1c0>;
760	};
761
762	pinctrl_fec: fecgrp {
763		fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x40000044>,
764			   <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x40000044>,
765			   <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x90>,
766			   <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x90>,
767			   <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x90>,
768			   <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x90>,
769			   <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC	0x90>,
770			   <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90>,
771			   <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0	0x12>,
772			   <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1	0x12>,
773			   <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2	0x12>,
774			   <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3	0x12>,
775			   <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x12>,
776			   <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC	0x14>;
777	};
778
779	pinctrl_fec_event: fecevtgrp {
780		fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN	0x100>,
781			   <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x1c0>;
782	};
783
784	pinctrl_fec_phy: fecphygrp {
785		fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x100>,
786			   <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x1c0>;
787	};
788
789	pinctrl_fec_phyalt: fecphyaltgrp {
790		fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24		0x180>,
791			   <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25		0x180>;
792	};
793
794	pinctrl_gpiobutton: gpiobuttongrp {
795		fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26		0x10>,
796			   <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27		0x10>;
797	};
798
799	pinctrl_gpioled: gpioledgrp {
800		fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05	0x14>,
801			   <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04		0x14>,
802			   <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03		0x14>;
803	};
804
805	pinctrl_gpio1: gpio1grp {
806		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x10>,
807			   <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x10>,
808			   <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x10>,
809			   <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x10>,
810			   <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x80>,
811			   <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x80>,
812			   <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x80>,
813			   <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x80>;
814	};
815
816	pinctrl_gpio4: gpio4grp {
817		fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20		0x180>,
818			   <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x180>;
819	};
820
821	pinctrl_hdmi: hdmigrp {
822		fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c2>,
823			   <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c2>,
824			   <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD	0x40000010>,
825			   <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC	0x40000010>;
826	};
827
828	pinctrl_hoggpio2: hoggpio2grp {
829		fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x140>,
830			   <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10	0x140>,
831			   <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x140>;
832	};
833
834	pinctrl_i2c2: i2c2grp {
835		fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001e2>,
836			   <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001e2>;
837	};
838
839	pinctrl_i2c2_gpio: i2c2-gpiogrp {
840		fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001e2>,
841			   <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001e2>;
842	};
843
844	pinctrl_i2c4: i2c4grp {
845		fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001e2>,
846			   <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001e2>;
847	};
848
849	pinctrl_i2c4_gpio: i2c4-gpiogrp {
850		fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x400001e2>,
851			   <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x400001e2>;
852	};
853
854	pinctrl_i2c6: i2c6grp {
855		fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL		0x400001e2>,
856			   <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA		0x400001e2>;
857	};
858
859	pinctrl_i2c6_gpio: i2c6-gpiogrp {
860		fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02		0x400001e2>,
861			   <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03		0x400001e2>;
862	};
863
864	pinctrl_lvdsdisplay: lvdsdisplaygrp {
865		fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x10>; /* Power enable */
866	};
867
868	pinctrl_pcf85063: pcf85063grp {
869		fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x80>;
870	};
871
872	/* LVDS Backlight */
873	pinctrl_pwm2: pwm2grp {
874		fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT		0x14>;
875	};
876
877	/* FAN */
878	pinctrl_pwm3: pwm3grp {
879		fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT		0x14>;
880	};
881
882	pinctrl_pwmfan: pwmfangrp {
883		fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x80>; /* FAN RPM */
884	};
885
886	pinctrl_reg12v0: reg12v0grp {
887		fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06		0x140>; /* VCC12V enable */
888	};
889
890	pinctrl_regpwmfan: regpwmfangrp {
891		fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x80>;
892	};
893
894	pinctrl_sai3: sai3grp {
895		fsl,pins = <
896			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0x94
897			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0x94
898			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0x94
899			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0x94
900			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0x94
901		>;
902	};
903
904	pinctrl_tlv320aic3x04: tlv320aic3x04grp {
905		fsl,pins = <
906			/* CODEC RST# */
907			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29		0x180
908		>;
909	};
910
911	/* X61 */
912	pinctrl_uart1: uart1grp {
913		fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX		0x140>,
914			   <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX		0x140>;
915	};
916
917	/* X61 */
918	pinctrl_uart2: uart2grp {
919		fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX	0x140>,
920			   <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX	0x140>;
921	};
922
923	pinctrl_uart3: uart3grp {
924		fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX	0x140>,
925			   <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX	0x140>;
926	};
927
928	pinctrl_uart4: uart4grp {
929		fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140>,
930			   <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140>;
931	};
932
933	pinctrl_usb0: usb0grp {
934		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x1c0>,
935			   <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR	0x1c0>;
936	};
937
938	pinctrl_usbcon0: usb0congrp {
939		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x1c0>;
940	};
941
942	pinctrl_usbhub: usbhubgrp {
943		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x10>;
944	};
945
946	pinctrl_usdhc2: usdhc2grp {
947		fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x192>,
948			   <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d2>,
949			   <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d2>,
950			   <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d2>,
951			   <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d2>,
952			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d2>,
953			   <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0>;
954	};
955
956	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
957		fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194>,
958			   <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4>,
959			   <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4>,
960			   <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4>,
961			   <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4>,
962			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4>,
963			   <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0>;
964	};
965
966	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
967		fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194>,
968			   <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4>,
969			   <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4>,
970			   <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4>,
971			   <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4>,
972			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4>,
973			   <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0>;
974	};
975
976	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
977		fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c0>;
978	};
979};
980