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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v5-iwb.yaml14 The GICv5 architecture defines the guidelines to implement GICv5
17 The GICv5 specification can be found at
20 GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible
21 for translating wire signals into interrupt messages to the GICv5 ITS.
H A Darm,gic-v5.yaml14 The GICv5 architecture defines the guidelines to implement GICv5
17 The GICv5 specification can be found at
20 The GICv5 architecture is composed of multiple components:
81 GICv5 has one or more Interrupt Routing Services (IRS) that are
135 GICv5 has zero or more Interrupt Translation Services (ITS) that are
176 GICv5 ITS has one or more translate register frames.
/linux/tools/testing/selftests/kvm/arm64/
H A Dno-vgic.c3 // Check that, on a GICv3-capable system (GICv3 native, or GICv5 with
5 // of the sysregs generating an UNDEF exception. Do the same for GICv5
6 // on a GICv5 host.
154 "GICv5 wrongly advertised"); in guest_code_gicv5()
157 * Try all GICv5 instructions, and fail if we don't get an UNDEF. in guest_code_gicv5()
280 "Neither GICv3 nor GICv5 supported."); in main()
293 pr_info("No GICv5 support: skipping no-vgic-v5 test\n"); in main()
H A Dvgic_v5.c168 TEST_ASSERT(ret == 0, "Failed to test GICv5 PPIs"); in test_vgic_v5_ppis()
220 pr_info("No GICv5 support; Not running GIC_v5 tests.\n"); in main()
/linux/drivers/irqchip/
H A Dirq-gic-v5-iwb.c5 #define pr_fmt(fmt) "GICv5 IWB: " fmt
173 .name = "GICv5-IWB",
290 .name = "GICv5 IWB",
H A Dirq-gic-v5-irs.c6 #define pr_fmt(fmt) "GICv5 IRS: " fmt
74 /* Taken from GICv5 specifications 10.2.1.13 IRS_IST_BASER */ in gicv5_irs_init_ist_linear()
138 /* Taken from GICv5 specifications 10.2.1.13 IRS_IST_BASER */ in gicv5_irs_init_ist_two_level()
350 * Follow GICv5 specification recommendation to opt in for two in gicv5_irs_init_ist()
744 pr_err("%pOF: unable to map GICv5 IRS registers\n", node); in gicv5_irs_of_init()
923 r = gic_request_region(irs->config_base_address, ACPI_GICV5_IRS_MEM_SIZE, "GICv5 IRS"); in gic_acpi_parse_madt_irs()
H A Dirq-gic-v5-its.c6 #define pr_fmt(fmt) "GICv5 ITS: " fmt
581 * We expect a GICv5 implementation requiring a large number of in gicv5_its_alloc_devtab_linear()
727 .name = "GICv5-ITS-MSI",
1208 pr_err("%pOF: unable to map GICv5 ITS_CONFIG_FRAME\n", node); in gicv5_its_init()
1263 pr_err("ITS@%pa: Unable to allocate GICv5 ITS translate domain token\n", in gic_acpi_parse_madt_its_translate()
1271 pr_err("ITS@%pa: Unable to register GICv5 ITS domain token (ITS TRANSLATE FRAME ID %d) to IORT\n", in gic_acpi_parse_madt_its_translate()
1314 if (!request_mem_region(res.start, resource_size(&res), "GICv5 ITS")) in gic_acpi_parse_madt_its()
1319 pr_err("ITS@%pa: Unable to allocate GICv5 ITS domain token\n", in gic_acpi_parse_madt_its()
/linux/include/linux/irqchip/
H A Darm-vgic-info.h18 /* Full GICv5, optionally with v3 compat */
/linux/arch/arm64/kvm/vgic/
H A Dvgic-init.c186 * We now know that we have a GICv5. The Arch Timer PPI interrupts may in kvm_vgic_create()
325 /* Register the GICv5-specific PPI ops */ in vgic_v5_allocate_private_irq()
H A Dvgic.c89 /* Non-private IRQs are not yet implemented for GICv5 */ in vgic_get_irq()
1101 * required for GICv3-on-GICv3, GICv2-on-GICv3, GICv3-on-GICv5, and the in vgic_restore_state()
/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst16 Creating a guest GICv3 device requires a host GICv3 host, or a GICv5 host with
/linux/arch/arm64/kvm/
H A Darm.c1516 /* Build a GICv5-style IntID here */ in kvm_vm_ioctl_irq_line()
1529 /* Build a GICv5-style IntID here */ in kvm_vm_ioctl_irq_line()
2453 kvm_err("NV support requires GICv3 or GICv5 with legacy support, giving up\n"); in init_subsystems()
H A Dsys_regs.c693 * Note: for GICv5 the mimic the way that the num_pri_bits and in access_gicv5_idr0()
713 * For GICv5 VMs, the IAFFID value is the same as the VPE ID. The VPE ID in access_gicv5_iaffid()
5811 * On GICv5 hardware that supports FEAT_GCIE_LEGACY we can run in kvm_finalize_sys_regs()
5812 * both GICv3- and GICv5-based guests. Therefore, we initially in kvm_finalize_sys_regs()
5826 * unmodified on compatible GICv5 hosts, and avoids the inverse in kvm_finalize_sys_regs()
5827 * problem for GICv5-based guests in the future. in kvm_finalize_sys_regs()
H A Dnested.c1566 /* GICv5 is not yet supported for NV */ in limit_nv_id_reg()
/linux/drivers/acpi/
H A Dbus.c1252 message = "GICv5"; in acpi_bus_init_irq()
/linux/arch/arm64/include/asm/
H A Dkvm_host.h819 /* PPI state tracking for GICv5-based guests */
H A Dsysreg.h1043 * Definitions for GICv5 instructions
/linux/arch/arm64/kernel/
H A Dcpufeature.c3147 .desc = "GICv5 CPU interface",
3154 .desc = "GICv5 Legacy vCPU interface",
/linux/Documentation/virt/kvm/
H A Dapi.rst912 in-kernel GICv5: SPI, irq_id between 0 and 65535 (incl.)
915 in-kernel GICv5: PPI, irq_id between 0 and 127 (incl.)