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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v5-iwb.yaml14 The GICv5 architecture defines the guidelines to implement GICv5
17 The GICv5 specification can be found at
20 GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible
21 for translating wire signals into interrupt messages to the GICv5 ITS.
H A Darm,gic-v5.yaml14 The GICv5 architecture defines the guidelines to implement GICv5
17 The GICv5 specification can be found at
20 The GICv5 architecture is composed of multiple components:
81 GICv5 has one or more Interrupt Routing Services (IRS) that are
135 GICv5 has zero or more Interrupt Translation Services (ITS) that are
176 GICv5 ITS has one or more translate register frames.
/linux/drivers/irqchip/
H A Dirq-gic-v5.c6 #define pr_fmt(fmt) "GICv5: " fmt
134 * Reference: I_ZLTKB/R_YRGMH GICv5 specification - section 2.9.1. in gicv5_ppi_irq_mask()
183 * Reference: I_ZLTKB/R_YRGMH GICv5 specification - section 2.9.1. in gicv5_ppi_irq_unmask()
524 .name = "GICv5-PPI",
536 .name = "GICv5-SPI",
551 .name = "GICv5-LPI",
564 .name = "GICv5-IPI",
945 "GICv5 system components present but CPU does not have FEAT_GCIE")) in gicv5_starting_cpu()
958 "irqchip/arm/gicv5:starting", in gicv5_smp_init()
1080 pr_warn("cannot find GICv5 virtual CPU interface maintenance interrupt\n"); in gic_of_setup_kvm_info()
H A Dirq-gic-v5-iwb.c5 #define pr_fmt(fmt) "GICv5 IWB: " fmt
159 .name = "GICv5-IWB",
270 .name = "GICv5 IWB",
H A Dirq-gic-v5-irs.c6 #define pr_fmt(fmt) "GICv5 IRS: " fmt
73 /* Taken from GICv5 specifications 10.2.1.13 IRS_IST_BASER */ in gicv5_irs_init_ist_linear()
137 /* Taken from GICv5 specifications 10.2.1.13 IRS_IST_BASER */ in gicv5_irs_init_ist_two_level()
349 * Follow GICv5 specification recommendation to opt in for two in gicv5_irs_init_ist()
703 pr_err("%pOF: unable to map GICv5 IRS registers\n", node); in gicv5_irs_init()
H A Dirq-gic-v5-its.c6 #define pr_fmt(fmt) "GICv5 ITS: " fmt
579 * We expect a GICv5 implementation requiring a large number of in gicv5_its_alloc_devtab_linear()
725 .name = "GICv5-ITS-MSI",
1200 pr_err("%pOF: unable to map GICv5 ITS_CONFIG_FRAME\n", node); in gicv5_its_init()
H A Dirq-gic-its-msi-parent.c195 * in GICv5 (where the msi controller nodes are the in of_v5_pmsi_get_msi_info()
/linux/include/linux/irqchip/
H A Darm-vgic-info.h18 /* Full GICv5, optionally with v3 compat */
39 /* v3 compat support (GICv5 hosts, only) */
/linux/arch/arm64/kvm/vgic/
H A Dvgic-v5.c10 * Currently only supports GICv3-based VMs on a GICv5 host, and hence only
/linux/include/kvm/
H A Darm_vgic.h41 VGIC_V5, /* Newer, fancier GICv5 */
84 /* GICv3 compat mode on a GICv5 host */
/linux/arch/arm64/kvm/hyp/
H A Dvgic-v3-sr.c299 * GICv5 BET0 FEAT_GCIE_LEGACY doesn't include ICC_SRE_EL2. This is due in __vgic_v3_activate_traps()
333 * Can be dropped in the future when GICv5 spec is relaxed. See comment in __vgic_v3_deactivate_traps()
445 * ICH_VTR_EL2. ICC_IDR0_EL1 is only implemented on a GICv5 in __vgic_v3_get_gic_config()
446 * system, so we first check if we have GICv5 support. in __vgic_v3_get_gic_config()
/linux/Documentation/arch/arm64/
H A Dbooting.rst226 For systems with a GICv5 interrupt controller to be used in v5 mode:
265 - The DT or ACPI tables must describe a GICv5 interrupt controller.
/linux/arch/arm64/include/asm/
H A Del2_setup.h168 /* GICv5 system register access */
H A Dsysreg.h1082 * Definitions for GICv5 instructions
/linux/arch/arm64/kernel/
H A Dcpufeature.c3153 .desc = "GICv5 CPU interface",
/linux/arch/arm64/kvm/
H A Dsys_regs.c2105 * If we are running on a GICv5 host and support FEAT_GCIE_LEGACY, then in set_id_aa64pfr0_el1()