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/linux/tools/testing/selftests/kvm/arm64/
H A Dno-vgic-v3.c
H A Dno-vgic.c3 // Check that, on a GICv3-capable system (GICv3 native, or GICv5 with
4 // FEAT_GCIE_LEGACY), not configuring GICv3 correctly results in all
93 "GICv3 wrongly advertised"); in guest_code_gicv3()
96 * Access all GICv3 registers, and fail if we don't get an UNDEF. in guest_code_gicv3()
281 "Neither GICv3 nor GICv5 supported."); in main()
287 pr_info("No GICv3 support: skipping no-vgic-v3 test\n"); in main()
H A Dvgic_init.c137 * ARM_VGIC (GICv2 or GICv3) device gets created with an overlapping
139 * used hence the overlap. In the case of GICv3, A RDIST region is set at @0x0
211 "attempt to mix GICv3 REDIST and REDIST_REGION"); in subtest_dist_rdist()
1017 print_skip("No GICv2 nor GICv3 support"); in main()
/linux/arch/arm64/boot/dts/arm/
H A Dfoundation-v8-gicv3-psci.dts4 * ARMv8 Foundation model DTS (GICv3+PSCI configuration)
8 #include "foundation-v8-gicv3.dtsi"
H A Dfoundation-v8-gicv3.dts5 * ARMv8 Foundation model DTS (GICv3 configuration)
9 #include "foundation-v8-gicv3.dtsi"
H A Dfoundation-v8-gicv3.dtsi4 * ARMv8 Foundation model DTS (GICv3 configuration)
/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst14 possible to create both a GICv3 and GICv2 on the same VM.
16 Creating a guest GICv3 device requires a host GICv3 host, or a GICv5 host with
25 Base address in the guest physical address space of the GICv3 distributor
30 Base address in the guest physical address space of the GICv3
106 in the GICv3/4 specs. Getting or setting such a register has the same
169 rules are documented in the GICv3 specification descriptions of the ICPENDR
H A Darm-vgic.rst16 GICv3 implementations with hardware compatibility support allow creating a
17 guest GICv2 through this interface. For information on creating a guest GICv3
19 create both a GICv3 and GICv2 device on the same VM.
/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dbooting.txt191 对于拥有 GICv3 中断控制器并以 v3 模式运行的系统：
198 - 设备树（DT）或 ACPI 表必须描述一个 GICv3 中断控制器。
200 对于拥有 GICv3 中断控制器并以兼容（v2）模式运行的系统：
H A Dsilicon-errata.txt74 | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dbooting.txt195 對於擁有 GICv3 中斷控制器並以 v3 模式運行的系統：
202 - 設備樹（DT）或 ACPI 表必須描述一個 GICv3 中斷控制器。
204 對於擁有 GICv3 中斷控制器並以兼容（v2）模式運行的系統：
H A Dsilicon-errata.txt78 | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
/linux/include/linux/irqchip/
H A Darm-vgic-info.h16 /* Full GICv3, optionally with v2 compat */
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsocionext,synquacer-exiu.yaml15 level-high type GICv3 SPIs.
/linux/drivers/irqchip/
H A Dirq-gic-v4.c18 * intricacies of GICv3, GICv4, and how a guest's view of a GICv3 gets
H A Dirq-gic-common.c111 * alone as they are in the redistributor registers on GICv3. in gic_dist_config()
H A Dirq-gic-v3-mbi.c7 #define pr_fmt(fmt) "GICv3: " fmt
H A Dirq-gic-v3-its.c2304 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n", in gic_check_reserved_range()
2349 pr_info("GICv3: using LPI property table @%pa\n", in its_setup_lpi_prop_table()
3083 pr_info("GICv3: Using preallocated redistributor tables\n"); in allocate_lpi_tables()
3276 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n", in its_cpu_init_lpis()
5395 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n", in redist_disable_lpis()
5735 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", in gic_acpi_parse_madt_its()
5743 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", in gic_acpi_parse_madt_its()
5821 "irqchip/arm/gicv3/memreserve:online", in its_lpi_memreserve_init()
/linux/tools/testing/selftests/arm64/fp/
H A DREADME76 --irqchip=gicv3. New kvmtool defaults to that if appropriate, but I
/linux/drivers/pci/controller/
H A Dpcie-iproc.c238 * GICv3 ITS)
252 * programmed. When ARM GICv3 ITS is used, this should be programmed
1226 * Check if 'msi-map' points to ARM GICv3 ITS, which is the only in iproce_pcie_get_msi()
1234 /* derive GITS_TRANSLATER address from GICv3 */ in iproce_pcie_get_msi()
1289 /* steering MSI to GICv3 ITS */ in iproc_pcie_paxc_v2_msi_steer()
/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v2.c392 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_read_apr()
418 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_write_apr()
H A Dvgic-mmio-v3.c376 /* report a GICv3 compliant implementation */ in vgic_mmio_read_v3_idregs()
601 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
1091 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
H A Dvgic-debug.c153 seq_printf(s, "vgic_model:\t%s\n", v3 ? "GICv3" : "GICv2"); in print_dist_state()
/linux/arch/arm/kernel/
H A Dhyp-stub.S165 @ Check whether GICv3 system registers are available
/linux/Documentation/virt/hyperv/
H A Dvpci.rst210 arm64 guest VMs because it does not emulate a GICv3 ITS.

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