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/linux/arch/arm64/boot/dts/broadcom/
H A Dbcm2712.dtsi11 interrupt-parent = <&gicv2>;
353 gicv2: interrupt-controller@7fff9000 {
559 interrupt-parent = <&gicv2>;
564 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
565 <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
566 <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
567 <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
596 interrupt-parent = <&gicv2>;
601 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
602 <0 0 0 2 &gicv2 GIC_SP
337 gicv2: interrupt-controller@7fff9000 { global() label
[all...]
/linux/Documentation/virt/kvm/devices/
H A Darm-vgic.rst17 guest GICv2 through this interface. For information on creating a guest GICv3
19 create both a GICv3 and GICv2 device on the same VM.
58 GICv2 specs. Getting or setting such a register has the same effect as
65 GICv2 is changed in a way directly observable by the guest or userspace.
92 defined in the GICv2 specs. Getting or setting such a register has the
96 fixed format for our implementation that fits with the model of a "GICv2
112 similar to GICv2's GICH_APR.
H A Darm-vgic-v3.rst14 possible to create both a GICv3 and GICv2 on the same VM.
/linux/arch/arm64/boot/dts/arm/
H A Dfoundation-v8-psci.dts4 * ARMv8 Foundation model DTS (GICv2+PSCI configuration)
8 #include "foundation-v8-gicv2.dtsi"
H A Dfoundation-v8.dts5 * ARMv8 Foundation model DTS (GICv2 configuration)
9 #include "foundation-v8-gicv2.dtsi"
H A Dfoundation-v8-gicv2.dtsi4 * ARMv8 Foundation model DTS (GICv2 configuration)
/linux/include/linux/irqchip/
H A Darm-vgic-info.h14 /* Full GICv2 */
27 /* GICv2 GICC VA */
/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v2.c20 * Revision 1: Report GICv2 interrupts as group 0 instead of group 1
380 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_read_apr()
392 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_read_apr()
406 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_write_apr()
418 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_write_apr()
H A Dvgic-init.c33 * structures. Can be executed lazily for GICv2.
79 * which had no chance yet to check the availability of the GICv2 in kvm_vgic_create()
263 * initialization when using a virtual GICv2. in kvm_vgic_vcpu_nv_init()
648 * is a GICv2. A GICv3 must be explicitly initialized by userspace using the in kvm_vgic_map_resources()
659 * for the legacy case of a GICv2. Any other type must in kvm_vgic_map_resources()
H A Dvgic-v2.c286 /* The GICv2 LR only holds five bits of priority. */ in vgic_v2_compute_lr()
331 /* The GICv2 LR only holds five bits of priority. */ in vgic_v2_populate_lr()
488 kvm_err("GICv2 not supported in protected mode\n"); in vgic_v2_probe()
527 kvm_err("Cannot register GICv2 KVM device\n"); in vgic_v2_probe()
H A Dvgic-v3.c252 * deactivating a GICv2 SGI. in vgic_v3_deactivate()
270 /* GICv2 SGI: check that the cpuid matches */ in vgic_v3_deactivate()
486 * If we are emulating a GICv3, we do it in an non-GICv2-compatible in vgic_v3_reset()
990 kvm_err("Cannot register GICv2 KVM device.\n"); in vgic_v3_probe()
1003 kvm_info("disabling GICv2 emulation\n"); in vgic_v3_probe()
H A Dvgic.c1022 * - GICv2 SGIs with multiple sources are injected one source at a time, as in vgic_flush_lr_state()
1074 * GICv2 can always be accessed from the kernel because it is in vgic_save_state()
1133 * required for GICv3-on-GICv3, GICv2-on-GICv3, GICv3-on-GICv5, and the in vgic_flush_state()
H A Dvgic-debug.c153 seq_printf(s, "vgic_model:\t%s\n", v3 ? "GICv3" : "GICv2"); in print_dist_state()
/linux/tools/testing/selftests/kvm/arm64/
H A Dvgic_init.c165 * ARM_VGIC (GICv2 or GICv3) device gets created with an overlapping in subtest_dist_rdist()
166 * DIST/REDIST (or DIST/CPUIF for GICv2). Assumption is 4 vcpus are going to be in subtest_dist_rdist()
168 * and a DIST region is set @0x70000. The GICv2 case sets a CPUIF @0x0 and a in subtest_dist_rdist()
175 struct vgic_region_attr rdist; /* CPU interface in GICv2*/ in subtest_dist_rdist()
1117 print_skip("No GICv2 nor GICv3 support");
H A Dvgic_irq.c40 * more priority levels. Also note that 32 is the minimum for GICv3 and GICv2.
/linux/Documentation/devicetree/bindings/gpio/
H A Dapm,xgene-gpio-sb.yaml22 | (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
/linux/arch/arm64/kernel/
H A Dimage-vars.h111 /* Static key indicating whether GICv3 has GICv2 compatibility */
/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dbooting.txt205 - 设备树（DT）或 ACPI 表必须描述一个 GICv2 中断控制器。
/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dbooting.txt209 - 設備樹（DT）或 ACPI 表必須描述一個 GICv2 中斷控制器。
/linux/Documentation/arch/arm64/
H A Dbooting.rst294 - The DT or ACPI tables must describe a GICv2 interrupt controller.
/linux/drivers/vfio/pci/
H A Dvfio_pci_core.c1864 * regions like the GICv2 VCPU interface can trigger uncontained in vfio_pci_core_mmap()
/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt2737 of a GICv2 controller even if the memory range