Searched full:gics (Results 1 – 4 of 4) sorted by relevance
144 * chips and call this to register their GICs.
48 * "performance interrupt". Luckily, on compliant GICs the polarity is in arm_pmu_acpi_register_irq()
700 MADT for GICs are expected to be in synchronization. The _UID of the Device769 - Section 9.17: I/O APIC devices; all GICs must be enumerable via MADT
496 * because any nested/secondary GICs do not directly interface in gic_cpu_init()