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/linux/drivers/clk/qcom/
H A Dgpucc-sdm845.c63 { .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },
H A Dgpucc-sc7280.c92 { .fw_name = "gcc_gpu_gpll0_clk_src" },
106 { .fw_name = "gcc_gpu_gpll0_clk_src", },
H A Dgpucc-sm6350.c135 { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" },
154 { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" },
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,qcm2290-gpucc.yaml70 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
H A Dqcom,sm8450-gpucc.yaml99 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
/linux/include/dt-bindings/clock/
H A Dqcom,gcc-sc7180.h46 #define GCC_GPU_GPLL0_CLK_SRC 36 macro
H A Dqcom,sm7150-gcc.h44 #define GCC_GPU_GPLL0_CLK_SRC 32 macro
H A Dqcom,gcc-qcm2290.h94 #define GCC_GPU_GPLL0_CLK_SRC 84 macro
H A Dqcom,sar2130p-gcc.h35 #define GCC_GPU_GPLL0_CLK_SRC 25 macro
H A Dqcom,sm4450-gcc.h43 #define GCC_GPU_GPLL0_CLK_SRC 33 macro
H A Dqcom,gcc-sm6115.h81 #define GCC_GPU_GPLL0_CLK_SRC 73 macro
H A Dqcom,gcc-sc7280.h44 #define GCC_GPU_GPLL0_CLK_SRC 34 macro
H A Dqcom,sm6375-gcc.h108 #define GCC_GPU_GPLL0_CLK_SRC 97 macro
H A Dqcom,sm8550-gcc.h41 #define GCC_GPU_GPLL0_CLK_SRC 30 macro
H A Dqcom,gcc-sm6125.h123 #define GCC_GPU_GPLL0_CLK_SRC 114 macro
H A Dqcom,qcs8300-gcc.h55 #define GCC_GPU_GPLL0_CLK_SRC 45 macro
H A Dqcom,kaanapali-gcc.h44 #define GCC_GPU_GPLL0_CLK_SRC 34 macro
H A Dqcom,gcc-sdm845.h41 #define GCC_GPU_GPLL0_CLK_SRC 31 macro
H A Dqcom,gcc-sm8150.h47 #define GCC_GPU_GPLL0_CLK_SRC 37 macro
H A Dqcom,sm8650-gcc.h43 #define GCC_GPU_GPLL0_CLK_SRC 32 macro
H A Dqcom,gcc-sm8450.h55 #define GCC_GPU_GPLL0_CLK_SRC 43 macro
H A Dqcom,hawi-gcc.h41 #define GCC_GPU_GPLL0_CLK_SRC 31 macro
H A Dqcom,gcc-sm8350.h51 #define GCC_GPU_GPLL0_CLK_SRC 39 macro
H A Dqcom,gcc-sm8250.h44 #define GCC_GPU_GPLL0_CLK_SRC 34 macro
H A Dqcom,shikra-gcc.h120 #define GCC_GPU_GPLL0_CLK_SRC 110 macro

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