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Searched full:fchs (Results 1 – 19 of 19) sorted by relevance

/freebsd/sys/dev/amdsbwd/
H A Damd_chipset.h30 * various versions of Fusion Controller Hubs (FCHs). FCHs integrated into
37 * - several types of southbridges and FCHs:
40 * o FCHs where the controller has an ID of 0x780b1022 and a revision less
41 * than 0x41 (various variants of "Hudson" and "Bolton" as well as FCHs
43 * o FCHs where the controller has an ID of 0x790b1022 and a revision less
45 * - several types of FCHs:
46 * o FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022
49 * o FCHs where the controller has an ID of 0x790b1022 and a revision greater
/freebsd/share/man/man4/
H A Damdsbwd.462 AMD Axx/Hudson/Bolton FCHs
64 AMD FCHs integrated into Family 15h Models 60h-6Fh, 70h-7Fh Processors
66 AMD FCHs integrated into Family 16h Models 00h-0Fh, 30h-3Fh Processors
H A Dintpm.458 AMD Axx/Hudson/Bolton FCHs
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Darm,mhuv3.yaml70 FCHs are expected to behave as RAM which generates interrupts when writes
72 When FCE is implemented, the number of FCHs that an implementation of the
75 FCHs are numbered from 0 in ascending order.
76 Note that the number of FCHs and the word-size are implementation defined,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Schedule.td302 defm WriteFSign : X86SchedWritePair<ReadAfterVecLd>; // Floating point fabs/fchs.
H A DX86ScheduleZnver1.td846 // FCHS.
H A DX86ScheduleZnver2.td856 // FCHS.
H A DX86InstrFPStack.td262 defm CHS : FPUnary<fneg, MRM_E0, "fchs">;
H A DX86SchedBroadwell.td331 defm : BWWriteResPair<WriteFSign, [BWPort5], 1>; // Floating point fabs/fchs.
H A DX86SchedSkylakeClient.td318 defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs.
H A DX86FloatingPoint.cpp1237 /// R1 = fchs R2
H A DX86ScheduleZnver3.td944 …, [Zn3FPFMul01], 1, [2], 1>; // FIXME: latency not from llvm-exegesis // Floating point fabs/fchs.
H A DX86SchedSkylakeServer.td318 defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs.
H A DX86ScheduleZnver4.td955 …, [Zn4FPFMul01], 1, [2], 1>; // FIXME: latency not from llvm-exegesis // Floating point fabs/fchs.
H A DX86SchedIceLake.td323 defm : ICXWriteResPair<WriteFSign, [ICXPort0], 1>; // Floating point fabs/fchs.
H A DX86ISelLowering.cpp774 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS in X86TargetLowering()
775 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS in X86TargetLowering()
784 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS in X86TargetLowering()
785 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS in X86TargetLowering()
820 addLegalFPImmediate(TmpFlt); // FLD0/FCHS in X86TargetLowering()
828 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS in X86TargetLowering()
/freebsd/sys/i386/i386/
H A Ddb_disasm.c399 "fchs", "fabs", "", "", "ftst", "fxam", "", ""
/freebsd/sys/amd64/amd64/
H A Ddb_disasm.c493 "fchs", "fabs", "", "", "ftst", "fxam", "", ""
/freebsd/sys/cddl/dev/dtrace/x86/
H A Ddis_tables.c2697 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID,