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/freebsd/sys/contrib/device-tree/Bindings/devfreq/event/
H A Dexynos-ppmu.txt2 * Samsung Exynos PPMU (Platform Performance Monitoring Unit) device
4 The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
9 The Exynos PPMU driver uses the devfreq-event class to provide event data
14 - compatible: Should be "samsung,exynos-ppmu" or "samsung,exynos-ppmu-v2.
33 compatible = "samsung,exynos-ppmu";
39 compatible = "samsung,exynos-ppmu";
45 compatible = "samsung,exynos-ppmu";
51 compatible = "samsung,exynos-ppmu";
59 compatible = "samsung,exynos-ppmu";
123 compatible = "samsung,exynos-ppmu-v2";
[all …]
H A Dsamsung,exynos-ppmu.yaml4 $id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
7 title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)
14 The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
19 Exynos PPMU driver uses the devfreq-event class to provide event data to
26 - samsung,exynos-ppmu
27 - samsung,exynos-ppmu-v2
79 compatible = "samsung,exynos-ppmu";
102 compatible = "samsung,exynos-ppmu";
117 compatible = "samsung,exynos-ppmu-v2";
122 compatible = "samsung,exynos
[all...]
/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dsamsung,exynos-bus.yaml4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
14 The Samsung Exynos SoC has many buses for data transfer between DRAM and
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
41 There are a little different composition among Exynos SoC because each Exynos
44 able to support the bus frequency for all Exynos SoCs.
47 to Exynos SoC::
163 - samsung,exynos-bus
[all …]
/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Dexynos-bus.txt1 * Generic Exynos Bus frequency device
3 The Samsung Exynos SoC has many buses for data transfer between DRAM
4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
5 for buses. Generally, each bus of Exynos SoC includes a source clock
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
30 There are a little different composition among Exynos SoC because each Exynos
33 is able to support the bus frequency for all Exynos SoCs.
36 - compatible: Should be "samsung,exynos-bus".
51 - exynos,saturation-ratio: the percentage value which is used to calibrate
67 Detailed correlation between sub-blocks and power line according to Exynos SoC:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dsamsung-phy.txt1 Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
30 Samsung Exynos SoC series Display Port PHY
41 Samsung S5P/Exynos SoC series USB PHY
66 meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
67 and Exynos 4212) it is as follows:
74 Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
79 For Exynos 4412 (compatible with Exynos 4212):
113 - samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
123 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
131 compatible: Should be "samsung,exynos-sataphy-i2c"
[all …]
H A Dsamsung,exynos5250-sata-phy.yaml36 samsung,exynos-sataphy-i2c-phandle:
48 - samsung,exynos-sataphy-i2c-phandle
63 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-bus.dtsi11 compatible = "samsung,exynos-bus";
19 compatible = "samsung,exynos-bus";
27 compatible = "samsung,exynos-bus";
35 compatible = "samsung,exynos-bus";
43 compatible = "samsung,exynos-bus";
51 compatible = "samsung,exynos-bus";
59 compatible = "samsung,exynos-bus";
67 compatible = "samsung,exynos-bus";
75 compatible = "samsung,exynos-bus";
83 compatible = "samsung,exynos-bus";
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5420.dtsi15 #include <dt-bindings/clock/exynos-audss-clk.h>
38 compatible = "samsung,exynos-bus";
45 compatible = "samsung,exynos-bus";
52 compatible = "samsung,exynos-bus";
59 compatible = "samsung,exynos-bus";
66 compatible = "samsung,exynos-bus";
73 compatible = "samsung,exynos-bus";
80 compatible = "samsung,exynos-bus";
86 compatible = "samsung,exynos-bus";
93 compatible = "samsung,exynos-bus";
[all …]
H A Dexynos4.dtsi20 #include <dt-bindings/clock/exynos-audss-clk.h>
782 compatible = "samsung,exynos-ppmu";
790 compatible = "samsung,exynos-ppmu";
798 compatible = "samsung,exynos-ppmu";
806 compatible = "samsung,exynos-ppmu";
814 compatible = "samsung,exynos-ppmu";
822 compatible = "samsung,exynos-ppmu";
830 compatible = "samsung,exynos-ppmu";
838 compatible = "samsung,exynos-ppmu";
844 compatible = "samsung,exynos-ppmu";
[all …]
H A Dexynos3250.dtsi47 compatible = "samsung,exynos-bus";
80 compatible = "samsung,exynos-bus";
88 compatible = "samsung,exynos-bus";
116 compatible = "samsung,exynos-bus";
124 compatible = "samsung,exynos-bus";
132 compatible = "samsung,exynos-bus";
160 compatible = "samsung,exynos-bus";
168 compatible = "samsung,exynos-bus";
190 compatible = "samsung,exynos-bus";
491 compatible = "samsung,exynos-sysmmu";
[all …]
H A Dexynos4210.dtsi32 compatible = "samsung,exynos-bus";
55 compatible = "samsung,exynos-bus";
78 compatible = "samsung,exynos-bus";
105 compatible = "samsung,exynos-bus";
125 compatible = "samsung,exynos-bus";
133 compatible = "samsung,exynos-bus";
141 compatible = "samsung,exynos-bus";
149 compatible = "samsung,exynos-bus";
169 compatible = "samsung,exynos-bus";
344 compatible = "samsung,exynos
[all...]
H A Dexynos4x12.dtsi32 compatible = "samsung,exynos-bus";
57 compatible = "samsung,exynos-bus";
65 compatible = "samsung,exynos-bus";
75 compatible = "samsung,exynos-bus";
96 compatible = "samsung,exynos-bus";
115 compatible = "samsung,exynos-bus";
125 compatible = "samsung,exynos-bus";
133 compatible = "samsung,exynos-bus";
152 compatible = "samsung,exynos-bus";
351 compatible = "samsung,exynos
[all...]
H A Dexynos5250.dtsi20 #include <dt-bindings/clock/exynos-audss-clk.h>
495 compatible = "samsung,exynos-sataphy-i2c";
837 compatible = "samsung,exynos-adc-v1";
848 compatible = "samsung,exynos-sysmmu";
858 compatible = "samsung,exynos-sysmmu";
869 compatible = "samsung,exynos-sysmmu";
880 compatible = "samsung,exynos-sysmmu";
890 compatible = "samsung,exynos-sysmmu";
901 compatible = "samsung,exynos-sysmmu";
911 compatible = "samsung,exynos-sysmmu";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dsamsung,exynos-adc.yaml4 $id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml#
7 title: Samsung Exynos Analog to Digital Converter (ADC)
16 - samsung,exynos-adc-v1 # Exynos5250
17 - samsung,exynos-adc-v2
88 - samsung,exynos-adc-v1
89 - samsung,exynos-adc-v2
132 compatible = "samsung,exynos-adc-v1";
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dsamsung,sysmmu.yaml7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
13 Samsung's Exynos architecture contains System MMUs that enables scattered
29 MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
42 const: samsung,exynos-sysmmu
90 compatible = "samsung,exynos-sysmmu";
/freebsd/sys/contrib/device-tree/Bindings/arm/samsung/
H A Dsamsung-soc.yaml7 title: Samsung S3C, S5P and Exynos SoC compatibles naming convention
23 pattern: "^samsung,.*(s3c|s5pv|exynos)[0-9a-z]+.*$"
31 pattern: "^samsung,(s3c|s5pv|exynos|exynosautov)[0-9]+-.*$"
H A Dexynos-chipid.yaml4 $id: http://devicetree.org/schemas/arm/samsung/exynos-chipid.yaml#
7 title: Samsung Exynos SoC series Chipid driver
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dsamsung,pinctrl-gpio-bank.yaml7 title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller.
H A Dsamsung,pinctrl-wakeup-interrupt.yaml7 title: Samsung S3C/S5P/Exynos SoC pin controller - wake-up interrupt controller
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller.
H A Dsamsung,pinctrl-pins-cfg.yaml7 title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller.
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsamsung,exynos-audss-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
7 title: Samsung Exynos SoC Audio SubSystem clock controller
17 include/dt-bindings/clock/exynos-audss-clk.h header.
/freebsd/sys/contrib/device-tree/Bindings/soc/samsung/
H A Dexynos-usi.yaml4 $id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
7 title: Samsung's Exynos USI (Universal Serial Interface)
69 <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
140 #include <dt-bindings/soc/samsung,exynos-usi.h>
H A Dexynos-chipid.yaml4 $id: http://devicetree.org/schemas/soc/samsung/exynos-chipid.yaml#
7 title: Samsung Exynos SoC series Chipid driver
/freebsd/sys/contrib/device-tree/Bindings/display/samsung/
H A Dsamsung,exynos-mixer.yaml4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-mixer.yaml#
7 title: Samsung Exynos SoC Mixer
16 Samsung Exynos SoC Mixer is responsible for mixing and blending multiple data
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dexynos-usb.txt1 Samsung Exynos SoC USB controller
3 The USB devices interface with USB controllers on Exynos SOCs.
93 The dwc3 core should be added as subnode to Exynos dwc3 glue.

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