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/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c667 tRPST = (last->emc_mrw & 0x80) >> 7; in tegra210_emc_r21021_set_clock()
737 emc_writel(emc, next->emc_mrw, EMC_MRW); in tegra210_emc_r21021_set_clock()
821 emc_writel(emc, value, EMC_MRW); in tegra210_emc_r21021_set_clock()
1252 ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1286 EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
1293 ccfifo_writel(emc, value, EMC_MRW, 0); in tegra210_emc_r21021_set_clock()
H A Dtegra210-emc.h87 #define EMC_MRW 0xe8 macro
850 u32 emc_mrw; member
/linux/arch/arm/mach-tegra/
H A Dsleep-tegra30.S23 #define EMC_MRW 0xe8 macro
550 str r2, [r0, #EMC_MRW]
560 str r2, [r0, #EMC_MRW]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml119 value of the EMC_MRW register for this set of timings