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Searched full:emc_cfg_2 (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/memory/tegra/
H A Dtegra124-emc.c137 #define EMC_CFG_2 0x2b8 macro
457 u32 emc_cfg_2; member
746 val = timing->emc_cfg_2; in tegra_emc_prepare_timing_change()
748 emc_ccfifo_writel(emc, val, EMC_CFG_2); in tegra_emc_prepare_timing_change()
811 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) in tegra_emc_prepare_timing_change()
812 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2); in tegra_emc_prepare_timing_change()
961 EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2") in load_one_timing_from_dt()
H A Dtegra20-emc.c85 #define EMC_CFG_2 0x2b8 macro
602 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
617 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
H A Dtegra210-emc.h140 #define EMC_CFG_2 0x2b8 macro
866 u32 emc_cfg_2; member
H A Dtegra30-emc.c99 #define EMC_CFG_2 0x2b8 macro
1127 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
1145 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
H A Dtegra210-emc-cc-r21021.c609 emc_writel(emc, next->emc_cfg_2, EMC_CFG_2); in tegra210_emc_r21021_set_clock()
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml109 value of the EMC_CFG_2 register for this set of timings