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Searched full:emc_cfg (Results 1 – 7 of 7) sorted by relevance

/linux/arch/arm/mach-tegra/
H A Dsleep-tegra30.S18 #define EMC_CFG 0xc macro
502 ldr r1, [r0, #EMC_CFG]
504 str r1, [r0, #EMC_CFG]
570 ldr r1, [r5, #0x0] @ restore EMC_CFG
571 str r1, [r0, #EMC_CFG]
592 .word TEGRA_EMC_BASE + EMC_CFG @0x0
603 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
611 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
619 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
831 ldr r1, [r0, #EMC_CFG]
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H A Dsleep-tegra20.S23 #define EMC_CFG 0xc macro
238 ldr r1, [r0, #EMC_CFG]
240 str r1, [r0, #EMC_CFG]
/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c245 u32 emc_cfg, emc_cfg_o, emc_cfg_update, value; in tegra210_emc_r21021_periodic_compensation() local
265 emc_cfg_o = emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
266 emc_cfg = emc_cfg_o & ~(EMC_CFG_DYN_SELF_REF | in tegra210_emc_r21021_periodic_compensation()
274 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
317 emc_writel(emc, emc_cfg_o, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
363 u32 emc_auto_cal_config, auto_cal_en, emc_cfg, emc_sel_dpd_ctrl; in tegra210_emc_r21021_set_clock() local
400 emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_set_clock()
417 emc_cfg = next->burst_regs[EMC_CFG_INDEX]; in tegra210_emc_r21021_set_clock()
418 emc_cfg &= ~(EMC_CFG_DYN_SELF_REF | EMC_CFG_DRAM_ACPD | in tegra210_emc_r21021_set_clock()
472 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
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H A Dtegra20-emc.c595 u32 emc_cfg, emc_dbg, emc_fbio, emc_adr_cfg; in emc_setup_hw() local
602 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
608 if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && in emc_setup_hw()
609 !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) { in emc_setup_hw()
616 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; in emc_setup_hw()
617 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
H A Dtegra210-emc.h26 #define EMC_CFG 0xc macro
H A Dtegra210-emc-core.c245 EMC_CFG,
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml104 value of the EMC_CFG register for this set of timings