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/linux/arch/arm64/kernel/
H A Dhyp-stub.S35 ventry elx_sync // Synchronous 64-bit EL1
36 ventry el1_irq_invalid // IRQ 64-bit EL1
37 ventry el1_fiq_invalid // FIQ 64-bit EL1
38 ventry el1_error_invalid // Error 64-bit EL1
40 ventry el1_sync_invalid // Synchronous 32-bit EL1
41 ventry el1_irq_invalid // IRQ 32-bit EL1
42 ventry el1_fiq_invalid // FIQ 32-bit EL1
43 ventry el1_error_invalid // Error 32-bit EL1
103 // Use the EL1 allocated stack, per-cpu offset
115 // Use EL2 translations for SPE & TRBE and disable access from EL1
[all …]
H A Dmte.c98 /* Enable MTE Sync Mode for EL1. */ in __mte_enable_kernel()
103 pr_info_once("MTE: enabled in %s mode at EL1\n", mode); in __mte_enable_kernel()
174 pr_info_once("MTE: enabled store only mode at EL1\n"); in mte_enable_kernel_store_only()
295 * Check if an async tag exception occurred at EL1. in mte_thread_switch()
/linux/arch/arm64/mm/
H A Dtrans_pgd-asm.S51 el1_sync_vector // Synchronous 64-bit EL1
52 invalid_vector hyp_stub_el1_irq_invalid // IRQ 64-bit EL1
53 invalid_vector hyp_stub_el1_fiq_invalid // FIQ 64-bit EL1
54 invalid_vector hyp_stub_el1_error_invalid // Error 64-bit EL1
56 invalid_vector hyp_stub_32b_el1_sync_invalid // Synchronous 32-bit EL1
57 invalid_vector hyp_stub_32b_el1_irq_invalid // IRQ 32-bit EL1
58 invalid_vector hyp_stub_32b_el1_fiq_invalid // FIQ 32-bit EL1
59 invalid_vector hyp_stub_32b_el1_error_invalid // Error 32-bit EL1
/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dperf.rst29 打开 VHE 时内核运行在 EL2，不打开 VHE 时内核运行在 EL1。客户机
30 内核总是运行在 EL1。
32 对于宿主机，该属性排除 EL1 和 VHE 上的 EL2。
34 对于客户机，该属性排除 EL1。请注意客户机从来不会运行在 EL2。
56 KVM 宿主机可能运行在 EL0（用户空间），EL1（non-VHE 内核）和
59 KVM 客户机可能运行在 EL0（用户空间）和 EL1（内核）。
69 对于 VHE 系统的 exclude_guest 属性排除 EL1，而对其中的 exclude_host
H A Dbooting.txt36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
162 CPU 必须处于 EL2（推荐，可访问虚拟化扩展）或非安全 EL1 模式下。
179 都一致的值。如果在 EL1 模式下进入内核，则 CNTHCTL_EL2 中的
195 - 若内核运行在 EL1：
203 - 若内核运行在 EL1：
H A Damu.rst56 - 提供低异常级别(EL2 和 EL1)访问 AMU 寄存器的能力。
66 EL0(用户空间) 访问 EL1(内核空间)。 因此，固件应该确保访问 AMU寄存器
95 由于以下原因，当前禁止从 KVM 客户端的用户空间(EL0)和内核空间(EL1)
/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dperf.rst30 打開 VHE 時內核運行在 EL2，不打開 VHE 時內核運行在 EL1。客戶機
31 內核總是運行在 EL1。
33 對於宿主機，該屬性排除 EL1 和 VHE 上的 EL2。
35 對於客戶機，該屬性排除 EL1。請注意客戶機從來不會運行在 EL2。
57 KVM 宿主機可能運行在 EL0（用戶空間），EL1（non-VHE 內核）和
60 KVM 客戶機可能運行在 EL0（用戶空間）和 EL1（內核）。
70 對於 VHE 系統的 exclude_guest 屬性排除 EL1，而對其中的 exclude_host
H A Dbooting.txt40 AArch64 異常模型由多個異常級（EL0 - EL3）組成，對於 EL0 和 EL1 異常級
166 CPU 必須處於 EL2（推薦，可訪問虛擬化擴展）或非安全 EL1 模式下。
183 都一致的值。如果在 EL1 模式下進入內核，則 CNTHCTL_EL2 中的
199 - 若內核運行在 EL1：
207 - 若內核運行在 EL1：
H A Damu.rst59 - 提供低異常級別(EL2 和 EL1)訪問 AMU 寄存器的能力。
69 EL0(用戶空間) 訪問 EL1(內核空間)。 因此，固件應該確保訪問 AMU寄存器
98 由於以下原因，當前禁止從 KVM 客戶端的用戶空間(EL0)和內核空間(EL1)
/linux/arch/arm64/kvm/hyp/vhe/
H A Dsysreg-sr.c20 /* These registers are common with EL1 */ in __sysreg_save_vel2_state()
34 * In VHE mode those registers are compatible between EL1 and EL2, in __sysreg_save_vel2_state()
67 * The EL1 view of CNTKCTL_EL1 has a bunch of RES0 bits where in __sysreg_save_vel2_state()
89 /* These registers are common with EL1 */ in __sysreg_restore_vel2_state()
103 * EL1 and EL2. in __sysreg_restore_vel2_state()
113 * CNTHCTL_EL2 only affects EL1 when running nVHE, so in __sysreg_restore_vel2_state()
155 * to host userspace or a different VCPU. EL1 registers only need to be
192 * example EL1 system registers on a VHE system where the host kernel
207 * When running a normal EL1 guest, we only load a new vcpu in __vcpu_load_switch_sysregs()
209 * speculative EL1&0 walks will have already completed. in __vcpu_load_switch_sysregs()
[all …]
H A Dtlb.c38 * vcpu state, we prevent the EL1 page-table walker to in enter_vmid_context()
54 * guest TLBs (EL1/EL0), we need to change one of these two in enter_vmid_context()
227 * - a TLBI targeting EL2 S1 is remapped to EL1 S1
/linux/arch/arm64/kvm/hyp/nvhe/
H A Dhyp-init.S37 ventry __do_hyp_init // Synchronous 64-bit EL1
38 ventry . // IRQ 64-bit EL1
39 ventry . // FIQ 64-bit EL1
40 ventry . // Error 64-bit EL1
42 ventry . // Synchronous 32-bit EL1
43 ventry . // IRQ 32-bit EL1
44 ventry . // FIQ 32-bit EL1
45 ventry . // Error 32-bit EL1
206 /* The core booted in EL1. KVM cannot be initialized on it. */
H A Dhost.S246 host_el1_sync_vect // Synchronous 64-bit EL1/EL0
247 invalid_host_el1_vect // IRQ 64-bit EL1/EL0
248 invalid_host_el1_vect // FIQ 64-bit EL1/EL0
249 invalid_host_el1_vect // Error 64-bit EL1/EL0
251 host_el1_sync_vect // Synchronous 32-bit EL1/EL0
252 invalid_host_el1_vect // IRQ 32-bit EL1/EL0
253 invalid_host_el1_vect // FIQ 32-bit EL1/EL0
254 invalid_host_el1_vect // Error 32-bit EL1/EL0
/linux/Documentation/arch/arm64/
H A Dbooting.rst13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
175 to have access to the virtualisation extensions), or in EL1.
197 kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
228 - If the kernel is entered at EL1 and EL2 is present:
276 - If the kernel is entered at EL1:
290 - If the kernel is entered at EL1:
303 - If the kernel is entered at EL1:
319 - If the kernel is entered at EL1:
350 - If EL2 is present and the kernel is entered at EL1:
363 - If the kernel is entered at EL1 and EL2 is present:
[all …]
H A Dperf.rst28 The kernel runs at EL2 with VHE and EL1 without. Guest kernels always run
29 at EL1.
31 For the host this attribute will exclude EL1 and additionally EL2 on a VHE
34 For the guest this attribute will exclude EL1. Please note that EL2 is
59 The KVM host may run at EL0 (userspace), EL1 (non-VHE kernel) and EL2 (VHE
62 The KVM guest may run at EL0 (userspace) and EL1 (kernel).
73 For VHE systems we exclude EL1 for exclude_guest and exclude both EL0,EL2
/linux/arch/arm64/kvm/hyp/
H A Dhyp-entry.S192 valid_vect el1_sync // Synchronous 64-bit EL1
193 valid_vect el1_irq // IRQ 64-bit EL1
194 valid_vect el1_fiq // FIQ 64-bit EL1
195 valid_vect el1_error // Error 64-bit EL1
197 valid_vect el1_sync // Synchronous 32-bit EL1
198 valid_vect el1_irq // IRQ 32-bit EL1
199 valid_vect el1_fiq // FIQ 32-bit EL1
200 valid_vect el1_error // Error 32-bit EL1
/linux/include/linux/firmware/intel/
H A Dstratix10-smc.h14 * service layer driver in normal world (EL1) to communicate with secure
24 * EL1 and EL3 communicates pointer as physical address rather than the
81 * Sync call used by service driver at EL1 to request the FPGA in EL3 to
101 * Async call used by service driver at EL1 to provide FPGA configuration data
127 * Sync call used by service driver at EL1 to track the completed write
151 * Sync call used by service driver at EL1 to inform secure world that all
171 * Sync call used by service driver at EL1 to query the physical address of
309 * Sync call used by service driver at EL1 to alert EL3 that a Double
327 * Sync call used by service driver at EL1 to report hard processor
345 * Sync call used by service driver at EL1 to query RSU retry counter
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A Dmmu.json9 …lk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1",
12 …alk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1"
15 …lk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1",
18 …alk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1"
H A Dexception.json12 …ructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1",
15 …tructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1"
/linux/arch/arm64/include/asm/
H A Del2_setup.h102 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
107 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1
112 mov x0, #3 // Enable EL1 physical timers
137 csel x2, xzr, x0, eq // all PMU counters from EL1
151 // use EL1&0 translation.
163 orr x2, x2, x0 // allow the EL1&0 translation
279 * executing in EL1.
383 /* Disable traps of access to GCS registers at EL0 and EL1 */
539 msr_s SYS_ZCR_EL2, x1 // length for EL1.
583 msr_s SYS_SMCR_EL2, x0 // length for EL1.
/linux/arch/arm64/kvm/hyp/include/hyp/
H A Dfault.h34 * rights. As such, we can use the EL1 translation regime, and in __translate_far_to_hpfar()
35 * don't have to distinguish between EL0 and EL1 access. in __translate_far_to_hpfar()
H A Dswitch.h57 * trap to EL1. Therefore, always make sure that for 32-bit guests, in __activate_traps_fpsimd32()
58 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit. in __activate_traps_fpsimd32()
303 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */ in __activate_traps_common()
310 * EL1 instead of being trapped to EL2. in __activate_traps_common()
365 * and vSError injection is enabled for EL1. Conveniently, for in ___activate_traps()
702 * an EL1 guest, or a non-HYP context of an EL2 guest). in kvm_handle_cntxct()
/linux/Documentation/virt/kvm/arm/
H A Dhyp-abi.rst25 SVC/EL1. These stubs are accessible by using a 'hvc #0' instruction,
67 EL1 to EL2 by enabling the VHE mode. This is conditioned by the CPU
/linux/arch/arm64/kvm/
H A Darch_timer.c531 * between EL1/vEL2 with NV. in timer_save_state()
776 * the EL1 timer state to memory, so let's call ECV to the rescue if in timer_set_traps()
942 * When NV2 is on, guest hypervisors have their EL1 timer register in kvm_timer_sync_nested()
954 * stored in the host EL1 timers, while the emulated EL1 in kvm_timer_sync_nested()
961 * notionally direct (we use the EL1 HW, as for VHE), while in kvm_timer_sync_nested()
962 * the EL1 registers access memory. in kvm_timer_sync_nested()
1414 /* First, do the virtual EL1 timer irq */ in kvm_timer_hyp_init()
1437 /* Now let's do the physical EL1 timer irq */ in kvm_timer_hyp_init()
H A Dhandle_exit.c67 * "If an SMC instruction executed at Non-secure EL1 is in handle_smc()
91 * at Non-secure EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than in handle_smc()
243 * - Guest usage of a ptrauth instruction (which the guest EL1 did not
282 * - the guest is in EL1, and we need to reinject the in kvm_handle_eret()

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