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/freebsd/sys/contrib/device-tree/Bindings/edac/
H A Dsocfpga-eccmgr.txt1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
15 L2 Cache ECC
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
22 On Chip RAM ECC
24 - compatible : Should be "altr,socfpga-ocram-ecc"
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/freebsd/crypto/openssl/test/recipes/30-test_evp_data/
H A Devppkey_kas.txt25 PrivateKey=KAS-ECC-CDH_P-192_C0
32 PublicKey=KAS-ECC-CDH_P-192_C0-PUBLIC
38 PrivPubKeyPair = KAS-ECC-CDH_P-192_C0:KAS-ECC-CDH_P-192_C0-PUBLIC
41 PublicKey=KAS-ECC-CDH_P-192_C0-Peer-PUBLIC
48 Derive=KAS-ECC-CDH_P-192_C0
49 PeerKey=KAS-ECC-CDH_P-192_C0-Peer-PUBLIC
54 Derive=KAS-ECC-CDH_P-192_C0
56 PeerKey=KAS-ECC-CDH_P-192_C0-Peer-PUBLIC
59 PrivateKey=KAS-ECC-CDH_P-192_C1
66 PublicKey=KAS-ECC-CDH_P-192_C1-PUBLIC
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H A Devppkey_ecc.txt56 # ECC CDH Alice with Bob peer
63 # ECC CDH Bob with Alice peer
76 # ECC CDH Bob with Malice peer
84 # ECC CDH Alice with Malice peer
134 # ECC CDH Alice with Bob peer
141 # ECC CDH Bob with Alice peer
154 # ECC CDH Bob with Malice peer
162 # ECC CDH Alice with Malice peer
212 # ECC CDH Alice with Bob peer
219 # ECC CDH Bob with Alice peer
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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dgpmc-nand.txt10 For NAND specific properties such as ECC modes or bus width, please refer to
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
31 "ham1" 1-bit Hamming ecc code
32 "bch4" 4-bit BCH ecc code
33 "bch8" 8-bit BCH ecc code
34 "bch16" 16-bit BCH ECC code
35 Refer below "How to select correct ECC scheme for your device ?"
47 locating ECC errors for BCHx algorithms. SoC devices which have
49 Using ELM for ECC error correction frees some CPU cycles.
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H A Dmtk-nand.txt5 the nand controller interface driver and the ECC engine driver.
23 - ecc-engine: Required ECC Engine node.
36 ecc-engine = <&bch>;
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
55 - nand-ecc-strength: Number of bits to correct per ECC step.
65 E : nand-ecc-strength.
71 Q : nand-ecc-step-size.
75 this number depends on max ecc step size
77 If max ecc step size supported is 1024,
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H A Dnand-chip.yaml25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
29 1/ The ECC engine is part of the NAND controller, in this
31 2/ The ECC engine is part of the NAND part (on-die), in this
33 3/ The ECC engine is external, in this case the phandle should
34 reference the specific ECC engine node.
37 nand-use-soft-ecc-engine:
38 description: Use a software ECC engine.
41 nand-no-ecc-engine:
42 description: Do not use any ECC correction.
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H A Drockchip,nand-controller.yaml66 nand-ecc-mode:
69 nand-ecc-step-size:
72 nand-ecc-strength:
75 The ECC configurations that can be supported are as follows.
76 NFC v600 ECC 16, 24, 40, 60
79 NFC v622 ECC 16, 24, 40, 60
82 NFC v800 ECC 16
85 NFC v900 ECC 16, 40, 60, 70
96 The NFC driver need this information to select ECC
100 rockchip,boot-ecc-strength:
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H A Dhisi504-nand.txt11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
20 The following ECC strength and step size are currently supported:
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
H A Draw-nand-chip.yaml16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
34 nand-ecc-placement:
36 Location of the ECC bytes. This location is unknown by default
37 but can be explicitly set to "oob", if all ECC bytes are
38 known to be stored in the OOB area, or "interleaved" if ECC
44 nand-ecc-mode:
46 Legacy ECC configuration mixing the ECC engine choice and
70 nand-ecc-maximize:
72 Whether or not the ECC strength should be maximized. The
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H A Dmediatek,nand-ecc-engine.yaml4 $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
7 title: MediaTek(MTK) SoCs NAND ECC engine
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
18 - mediatek,mt2701-ecc
19 - mediatek,mt2712-ecc
20 - mediatek,mt7622-ecc
21 - mediatek,mt7986-ecc
25 - description: Base physical address and size of ECC.
29 - description: ECC interrupt
56 bch: ecc@1100e000 {
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H A Dnvidia-tegra20-nand.txt25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
28 Supported values with "hw" ECC mode are: "rs", "bch".
31 - nand-ecc-strength: integer representing the number of bits to correct
32 per ECC step (always 512). Supported strength using HW ECC
36 - nand-ecc-maximize: See nand-controller.yaml
37 - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
60 nand-ecc-algo = "bch";
61 nand-ecc-strength = <8>;
H A Dmediatek,mtk-nfc.yaml37 ecc-engine:
38 description: device-tree node of the required ECC engine.
48 nand-ecc-mode:
63 nand-ecc-step-size:
65 nand-ecc-strength:
78 nand-ecc-step-size:
80 nand-ecc-strength:
93 nand-ecc-step-size:
95 nand-ecc-strength:
104 - ecc-engine
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H A Dmxicy,nand-ecc-engine.yaml4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
7 title: Macronix NAND ECC engine
14 const: mxicy,nand-ecc-engine-rev3
46 nand-ecc-engine = <&ecc_engine0>;
50 ecc_engine0: ecc@43c40000 {
51 compatible = "mxicy,nand-ecc-engine-rev3";
65 nand-ecc-engine = <&ecc_engine1>;
70 nand-ecc-engine = <&spi_controller1>;
74 ecc_engine1: ecc@43c40000 {
75 compatible = "mxicy,nand-ecc-engine-rev3";
H A Dbrcm,brcmnand.yaml131 nand-ecc-step-size:
137 expected for the ECC layout in use. This size, in
145 number of available options for its default ECC
149 brcm,nand-ecc-use-strap:
151 This property requires the host system to get the ECC related
153 the generic NAND ECC settings. This is a common hardware design
154 on BCMBCA based boards. This strap ECC option and generic NAND
155 ECC option can not be specified at the same time.
211 - brcm,nand-ecc-use-strap
216 nand-ecc-strength: false
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H A Dmarvell-nand.txt47 - nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
48 - nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
49 not using hardware ECC. Howerver, it may be added when using hardware
50 ECC for clarification but will be ignored by the driver because ECC
52 the NAND chip. This value may be overwritten with nand-ecc-strength
54 - nand-ecc-strength: see nand-controller.yaml.
55 - nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
59 patterns described in AN-379, "Marvell SoC NFC ECC".
78 nand-ecc-mode = "hw";
81 nand-ecc-strength = <4>;
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H A Ddenali,nand.yaml40 ecc: ECC circuit clock
44 - const: ecc
84 nand-ecc-strength:
88 nand-ecc-step-size:
101 nand-ecc-strength:
106 nand-ecc-step-size:
119 nand-ecc-strength:
123 nand-ecc-step-size:
143 clock-names = "nand", "nand_x", "ecc";
H A Ddavinci-nand.txt42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
48 - ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
58 - ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
86 nand-ecc-mode = "hw";
87 ti,davinci-ecc-bits = <4>;
H A Damlogic,meson-nand.yaml49 nand-ecc-mode:
52 nand-ecc-step-size:
55 nand-ecc-strength:
58 The ECC configurations that can be supported are as follows.
70 Number of pages starting from offset 0, where a special ECC
72 code. This ECC configuration uses 384 bytes data blocks.
86 nand-ecc-strength: [nand-ecc-step-size]
87 nand-ecc-step-size: [nand-ecc-strength]
H A Dvf610-nfc.txt17 there might be restrictions on maximum rates when using hardware ECC.
29 - nand-ecc-mode: see nand-controller.yaml
31 Required properties for hardware ECC:
32 - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
33 - nand-ecc-step-size: step size equals page size, currently only 2k pages are
54 nand-ecc-mode = "hw";
55 nand-ecc-strength = <32>;
56 nand-ecc-step-size = <2048>;
H A Dgpmi-nand.txt32 - fsl,use-minimum-ecc: Protect this NAND flash with the minimum ECC
33 strength required. The required ECC strength is
39 ECC scheme.
50 - nand-ecc-strength: integer representing the number of bits to correct
51 per ECC step. Needs to be a multiple of 2.
52 - nand-ecc-step-size: integer representing the number of data bytes
53 that are covered by a single ECC step. The driver
H A Datmel-nand.txt6 The NAND controller might be connected to an ECC engine.
27 - ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
51 * ECC engine (PMECC) bindings:
70 pmecc: ecc-engine@ffffc070 {
93 ecc-engine = <&pmecc>;
120 and hardware ECC controller if available.
121 If the hardware ECC is PMECC, it should contain address and size for
135 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
138 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
140 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dsynopsys.txt3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
9 These both ECC controllers correct single bit ECC errors and detect double bit
10 ECC errors.
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
H A Dsynopsys,ddrc-ecc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
15 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
18 The Zynq DDR ECC controller has an optional ECC support in half-bus width
21 These both ECC controllers correct single bit ECC errors and detect double bit
22 ECC errors.
H A Dsnps,dw-umctl2-ddrc.yaml16 be equipped with SEC/DEC ECC feature if DRAM data bus width is either
20 controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
37 ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,
48 - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
50 - const: ecc
51 - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
101 interrupt-names = "ecc";
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi343 clock-names = "nand", "nand_x", "ecc";
540 reset-names = "dwc2", "dwc2-ecc";
554 reset-names = "dwc2", "dwc2-ecc";
602 compatible = "altr,socfpga-s10-ecc-manager",
603 "altr,socfpga-a10-ecc-manager";
618 ocram-ecc@ff8cc000 {
619 compatible = "altr,socfpga-s10-ocram-ecc",
620 "altr,socfpga-a10-ocram-ecc";
622 altr,ecc-parent = <&ocram>;
626 usb0-ecc@ff8c4000 {
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