| /linux/drivers/pwm/ |
| H A D | pwm-ntxec.c | 16 * - The period and duty cycle can't be changed together in one atomic action.
44 * The time base used in the EC is 8MHz, or 125ns. Period and duty cycle are
57 int period, int duty) in ntxec_pwm_set_raw_period_and_duty_cycle() argument
62 * Changes to the period and duty cycle take effect as soon as the in ntxec_pwm_set_raw_period_and_duty_cycle()
65 * duty cycle is fully written. If, in such a case, the old duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
68 * To minimize the time between the changes to period and duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
74 { NTXEC_REG_DUTY_HIGH, ntxec_reg8(duty >> 8) }, in ntxec_pwm_set_raw_period_and_duty_cycle()
76 { NTXEC_REG_DUTY_LOW, ntxec_reg8(duty) }, in ntxec_pwm_set_raw_period_and_duty_cycle()
86 unsigned int period, duty; in ntxec_pwm_apply() local
93 duty = min_t(u64, state->duty_cycle, period); in ntxec_pwm_apply()
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| H A D | pwm-sunplus.c | 17 * - In .apply() PWM output need to write register FREQ and DUTY. When first write FREQ
18 * done and not yet write DUTY, it has short timing gap use new FREQ and old DUTY.
59 u32 dd_freq, duty, mode0, mode1; in sunplus_pwm_apply() local
102 /* cal and set pwm duty */ in sunplus_pwm_apply()
110 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX; in sunplus_pwm_apply()
116 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, in sunplus_pwm_apply()
118 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty; in sunplus_pwm_apply()
120 writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_apply()
131 u32 mode0, dd_freq, duty; in sunplus_pwm_get_state() local
139 duty = readl(priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_get_state()
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| H A D | pwm-renesas-tpu.c | 77 u16 duty; member
181 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty); in tpu_pwm_timer_start()
185 tpd->channel, tpd->duty, tpd->period); in tpu_pwm_timer_start()
227 tpd->duty = 0; in tpu_pwm_request()
251 u32 duty; in tpu_pwm_config() local
303 duty = mul_u64_u64_div_u64(clk_rate, duty_ns, in tpu_pwm_config()
306 duty = 0; in tpu_pwm_config()
309 "rate %u, prescaler %u, period %u, duty %u\n", in tpu_pwm_config()
310 clk_rate, 1 << (2 * prescaler), (u32)period, duty); in tpu_pwm_config()
317 tpd->duty = duty; in tpu_pwm_config()
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| H A D | pwm-sprd.c | 76 u32 val, duty, prescale; in sprd_pwm_get_state() local
100 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. in sprd_pwm_get_state()
103 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate in sprd_pwm_get_state()
111 duty = val & SPRD_PWM_DUTY_MSK; in sprd_pwm_get_state()
112 tmp = (prescale + 1) * NSEC_PER_SEC * duty; in sprd_pwm_get_state()
127 u32 prescale, duty; in sprd_pwm_config() local
133 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. in sprd_pwm_config()
140 duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns; in sprd_pwm_config()
149 * Note: Writing DUTY triggers the hardware to actually apply the in sprd_pwm_config()
150 * values written to MOD and DUTY to the output, so must keep writing in sprd_pwm_config()
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| H A D | pwm-atmel-tcb.c | 37 unsigned duty; /* PWM duty expressed in clk cycles */ member
80 tcbpwm->duty = 0; in atmel_tcb_pwm_request()
95 &tcbpwm->duty); in atmel_tcb_pwm_request()
99 &tcbpwm->duty); in atmel_tcb_pwm_request()
130 * If duty is 0 the timer will be stopped and we have to in atmel_tcb_pwm_disable()
137 if (tcbpwm->duty == 0) in atmel_tcb_pwm_disable()
184 * If duty is 0 the timer will be stopped and we have to in atmel_tcb_pwm_enable()
191 if (tcbpwm->duty == 0) in atmel_tcb_pwm_enable()
216 * If duty is 0 or equal to period there's no need to register in atmel_tcb_pwm_enable()
221 if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) { in atmel_tcb_pwm_enable()
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| H A D | pwm-rockchip.c | 40 unsigned long duty; member
84 tmp = readl_relaxed(pc->base + pc->data->regs.duty); in rockchip_pwm_get_state()
106 unsigned long period, duty; in rockchip_pwm_config() local
113 * Since period and duty cycle registers have a width of 32 in rockchip_pwm_config()
122 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); in rockchip_pwm_config()
125 * Lock the period and duty of previous configuration, then in rockchip_pwm_config()
126 * change the duty and period, that would not be effective. in rockchip_pwm_config()
135 writel(duty, pc->base + pc->data->regs.duty); in rockchip_pwm_config()
147 * the configuration of duty, period and polarity in rockchip_pwm_config()
234 .duty = 0x04,
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| H A D | pwm-jz4740.c | 106 * Set duty > period. This trick allows the TCU channels in TCU2 mode to in jz4740_pwm_disable()
129 unsigned long period, duty; in jz4740_pwm_apply() local
161 /* Calculate duty value */ in jz4740_pwm_apply()
164 duty = tmp; in jz4740_pwm_apply()
166 if (duty >= period) in jz4740_pwm_apply()
167 duty = period - 1; in jz4740_pwm_apply()
180 /* Set duty */ in jz4740_pwm_apply()
181 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), duty); in jz4740_pwm_apply()
194 * duty value, then becomes active until the timer reaches the period in jz4740_pwm_apply()
195 * value. In theory, we should then use (period - duty) as the real duty in jz4740_pwm_apply()
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| H A D | pwm-iqs620a.c | 9 * to the duty cycle or enable/disable state.
10 * - Changes to the duty cycle or enable/disable state take effect immediately
12 * - The device cannot generate a 0% duty cycle. For duty cycles below 1 / 256
84 * The duty cycle generated by the device is calculated as follows: in iqs620_pwm_apply()
89 * (inclusive). Therefore the lowest duty cycle the device can generate in iqs620_pwm_apply()
92 * For lower duty cycles (e.g. 0), the PWM output is simply disabled to in iqs620_pwm_apply()
122 * Since the device cannot generate a 0% duty cycle, requests to do so in iqs620_pwm_get_state()
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| H A D | pwm-pca9685.c | 135 /* Helper function to set the duty cycle ratio to duty/4096 (e.g. duty=2048 -> 50%) */
136 static void pca9685_pwm_set_duty(struct pwm_chip *chip, int channel, unsigned int duty) in pca9685_pwm_set_duty() argument
141 if (duty == 0) { in pca9685_pwm_set_duty()
145 } else if (duty >= PCA9685_COUNTER_RANGE) { in pca9685_pwm_set_duty()
159 * configured duty cycle / power output. in pca9685_pwm_set_duty()
165 off = (on + duty) % PCA9685_COUNTER_RANGE; in pca9685_pwm_set_duty()
202 /* Read ON register to calculate duty cycle of staggered output */ in pca9685_pwm_get_duty()
372 unsigned long long duty, prescale; in __pca9685_pwm_apply() local
414 duty = PCA9685_COUNTER_RANGE * state->duty_cycle; in __pca9685_pwm_apply()
415 duty = DIV_ROUND_UP_ULL(duty, state->period); in __pca9685_pwm_apply()
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| H A D | pwm-xilinx.c | 6 * - When changing both duty cycle and period, we may end up with one cycle
7 * with the old duty cycle and the new period. This is because the counters
13 * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
111 * duty cycle (% high time) than what was requested. in xilinx_pwm_apply()
121 /* Same thing for duty cycles */ in xilinx_pwm_apply()
127 * If we specify 100% duty cycle, we will get 0% instead, so decrease in xilinx_pwm_apply()
128 * the duty cycle count by one. in xilinx_pwm_apply()
133 /* Round down to 0% duty cycle for unrepresentable duty cycles */ in xilinx_pwm_apply()
184 * 100% duty cycle results in constant low output. This may be (very) in xilinx_pwm_get_state()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| H A D | fanpwm.c | 44 u32 divs, duty; in nvkm_fanpwm_get() local
47 ret = therm->func->pwm_get(therm, fan->func.line, &divs, &duty); in nvkm_fanpwm_get()
49 divs = max(divs, duty); in nvkm_fanpwm_get()
51 duty = divs - duty; in nvkm_fanpwm_get()
52 return (duty * 100) / divs; in nvkm_fanpwm_get()
63 u32 divs, duty; in nvkm_fanpwm_set() local
74 duty = ((divs * percent) + 99) / 100; in nvkm_fanpwm_set()
76 duty = divs - duty; in nvkm_fanpwm_set()
78 ret = therm->func->pwm_set(therm, fan->func.line, divs, duty); in nvkm_fanpwm_set()
91 u32 divs, duty; in nvkm_fanpwm_create() local
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| H A D | fan.c | 39 int duty; in nvkm_fan_update() local
52 /* check that we're not already at the target duty cycle */ in nvkm_fan_update()
53 duty = fan->get(therm); in nvkm_fan_update()
54 if (duty == target) { in nvkm_fan_update()
60 if (!immediate && duty >= 0) { in nvkm_fan_update()
65 if (duty < target) in nvkm_fan_update()
66 duty = min(duty + 3, target); in nvkm_fan_update()
67 else if (duty > target) in nvkm_fan_update()
68 duty = max(duty - 3, target); in nvkm_fan_update()
70 duty = target; in nvkm_fan_update()
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| H A D | base.c | 44 u16 duty, i; in nvkm_therm_update_trip() local
59 duty = cur_trip->fan_duty; in nvkm_therm_update_trip()
62 duty = 0; in nvkm_therm_update_trip()
66 return duty; in nvkm_therm_update_trip()
74 u16 duty; in nvkm_therm_compute_linear_duty() local
83 duty = (temp - linear_min_temp); in nvkm_therm_compute_linear_duty()
84 duty *= (therm->fan->bios.max_duty - therm->fan->bios.min_duty); in nvkm_therm_compute_linear_duty()
85 duty /= (linear_max_temp - linear_min_temp); in nvkm_therm_compute_linear_duty()
86 duty += therm->fan->bios.min_duty; in nvkm_therm_compute_linear_duty()
87 return duty; in nvkm_therm_compute_linear_duty()
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| /linux/Documentation/hwmon/ |
| H A D | dme1737.rst | 166 attribute that needs to be set to the maximum attainable RPM (fan at 100% duty-
178 manual mode, the fan speed is set by writing the duty-cycle value to the
180 current duty-cycle as set by the fan controller in the chip. All PWM outputs
191 duty-cycles: full, low, and min. Full is internally hard-wired to 255 (100%)
198 pwm[1-3]_auto_point2_pwm full-speed duty-cycle (255, i.e., 100%)
199 pwm[1-3]_auto_point1_pwm low-speed duty-cycle
200 pwm[1-3]_auto_pwm_min min-speed duty-cycle
208 The chip adjusts the output duty-cycle linearly in the range of auto_point1_pwm
211 auto_point1_temp_hyst value, the output duty-cycle is set to the auto_pwm_min
214 duty-cycle. If any of the temperatures rise above the auto_point3_temp value,
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| H A D | vt1211.rst | 181 Each PWM has 4 associated distinct output duty-cycles: full, high, low and
186 thermal thresholds exist that controls both PWMs output duty-cycles. The
194 PWM Auto Point PWM Output Duty-Cycle
196 pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255)
197 pwm[1-2]_auto_point3_pwm high speed duty-cycle
198 pwm[1-2]_auto_point2_pwm low speed duty-cycle
199 pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0)
212 PWM output duty-cycle based on the input temperature:
215 Thermal Threshold Output Duty-Cycle Output Duty-Cycle
218 - full speed duty-cycle full speed duty-cycle
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| H A D | nzxt-kraken3.rst | 26 Kraken 2023 models additionally expose the speed and duty of an optionally connected
29 Pump and fan duty control mode can be set through pwm[1-2]_enable, where 1 is
32 duty to 100%.
62 2 Curve control mode (applies the temp-PWM duty curve based on coolant temp)
72 pwm1 Pump duty (value between 0-255)
73 pwm1_enable Pump duty control mode (0: disabled, 1: manual, 2: curve)
74 pwm2 Fan duty (value between 0-255)
75 pwm2_enable Fan duty control mode (0: disabled, 1: manual, 2: curve)
76 temp[1-2]_auto_point[1-40]_pwm Temp-PWM duty curves (for pump and fan), related to coolant temp
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| H A D | lm93.rst | 109 a minimum pulse width of 5 clocks (at 22.5kHz => 6.25% duty cycle), and
110 a maximum pulse width of 80 clocks (at 22.5kHz => 99.88% duty cycle).
115 contains a value controlling the duty cycle for the PWM signal used when
117 indicating minimum duty cycle and 15 indicating maximum.
148 and pwm2 are used to set the manual duty cycle; each is an integer (0-255)
149 where 0 is 0% duty cycle, and 255 is 100%. Note that the duty cycle values
152 PWM mode is disabled, the value of pwm1 and pwm2 indicates the current duty
238 A spin-up cycle occurs when a PWM output is commanded from 0% duty cycle to
239 some value > 0%. The LM93 supports a minimum duty cycle during spin-up. These
241 file has the same representation as other PWM duty cycle values. The
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| /linux/Documentation/devicetree/bindings/regulator/ |
| H A D | pwm-regulator.yaml | 19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
29 appropriate duty-cycle values. This allows for a much more fine grained
31 make an assumption that a %50 duty-cycle value will cause the regulator
49 description: Voltage and Duty-Cycle table.
54 - description: duty-cycle in percent (%)
63 Integer value encoding the duty cycle unit. If not
75 Duty cycle values are expressed in pwm-dutycycle-unit.
104 * Inverted PWM logic, and the duty cycle range is limited
119 /* Voltage Duty-Cycle */
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| /linux/Documentation/devicetree/bindings/input/ |
| H A D | pwm-vibrator.yaml | 14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
39 direction-duty-cycle-ns:
41 Duty cycle of the direction PWM channel in nanoseconds,
58 direction-duty-cycle-ns = <1000000000>;
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| /linux/drivers/clk/meson/ |
| H A D | sclk-div.c | 12 * The duty cycle may also be set for the LR clock variant. The duty cycle
126 struct clk_duty *duty) in sclk_div_set_duty_cycle() argument
132 memcpy(&sclk->cached_duty, duty, sizeof(*duty)); in sclk_div_set_duty_cycle()
140 struct clk_duty *duty) in sclk_div_get_duty_cycle() argument
147 duty->num = 1; in sclk_div_get_duty_cycle()
148 duty->den = 2; in sclk_div_get_duty_cycle()
153 duty->num = hi + 1; in sclk_div_get_duty_cycle()
154 duty->den = sclk->cached_div; in sclk_div_get_duty_cycle()
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| /linux/drivers/hwmon/ |
| H A D | asus_rog_ryujin.c | 30 /* Cooler duty report offsets */
40 /* Controller duty report offsets */
100 u8 duty_input[3]; /* Pump, internal fan and controller fan duty in PWM */
223 /* Retrieve cooler duty */ in rog_ryujin_get_status()
230 /* Retrieve controller duty */ in rog_ryujin_get_status()
303 * Retrieve cooler duty since both pump and internal fan are set in rog_ryujin_write_fixed_duty()
321 /* Cooler pump duty */ in rog_ryujin_write_fixed_duty()
326 /* Cooler internal fan duty */ in rog_ryujin_write_fixed_duty()
339 * Controller fan duty (channel == 2). No need to retrieve current in rog_ryujin_write_fixed_duty()
340 * duty, so just send the command. in rog_ryujin_write_fixed_duty()
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| /linux/drivers/leds/rgb/ |
| H A D | leds-pwm-multicolor.c | 36 unsigned long long duty; in led_pwm_mc_set() local
45 duty = priv->leds[i].state.period; in led_pwm_mc_set()
46 duty *= mc_cdev->subled_info[i].brightness; in led_pwm_mc_set()
47 do_div(duty, cdev->max_brightness); in led_pwm_mc_set()
50 duty = priv->leds[i].state.period - duty; in led_pwm_mc_set()
52 priv->leds[i].state.duty_cycle = duty; in led_pwm_mc_set()
53 priv->leds[i].state.enabled = duty > 0; in led_pwm_mc_set()
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| /linux/include/trace/events/ |
| H A D | clk.h | 233 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
235 TP_ARGS(core, duty),
245 __entry->num = duty->num;
246 __entry->den = duty->den;
255 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
257 TP_ARGS(core, duty)
262 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
264 TP_ARGS(core, duty)
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| /linux/drivers/clk/ |
| H A D | clk-scmi.c | 183 static int scmi_clk_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) in scmi_clk_get_duty_cycle() argument
193 duty->num = val; in scmi_clk_get_duty_cycle()
194 duty->den = 100; in scmi_clk_get_duty_cycle()
197 "Failed to get duty cycle for clock ID %d\n", clk->id); in scmi_clk_get_duty_cycle()
203 static int scmi_clk_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) in scmi_clk_set_duty_cycle() argument
209 /* SCMI OEM Duty Cycle is expressed as a percentage */ in scmi_clk_set_duty_cycle()
210 val = (duty->num * 100) / duty->den; in scmi_clk_set_duty_cycle()
216 "Failed to set duty cycle(%u/%u) for clock ID %d\n", in scmi_clk_set_duty_cycle()
217 duty->num, duty->den, clk->id); in scmi_clk_set_duty_cycle()
313 /* Duty cycle */ in scmi_clk_ops_alloc()
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| /linux/Documentation/driver-api/thermal/ |
| H A D | cpu-idle-cooling.rst | 71 or decreased by modulating the duty cycle of the idle injection.
86 duty cycle 25%
90 the duty cycle percentage. When no mitigation is happening the cooling
91 device state is zero, meaning the duty cycle is 0%.
94 starting state is selected. With a fixed idle duration and the duty
98 The governor will change the cooling device state thus the duty cycle
114 duty cycle 33%
128 duty cycle 50%
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