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/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dclock_source.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
65 * Display Port HW De spread of Reference Clock related Parameters structure
70 /* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
87 /*> DP reference clock - calculated only for DP signal for specific cases*/
89 /*> Encoder object Id - needed by VBIOS Exec table*/
91 /*> signalType -> Encoder Mode - needed by VBIOS Exec table*/
93 /*> ControllerId - which controller using this PLL*/
96 /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
/linux/drivers/clk/
H A Dclk-renesas-pcie.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Renesas 9-series PCIe clock generator driver
6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
8 * - 9FGV0241
9 * - 9FGV0441
10 * - 9FGV0841
12 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
15 #include <linux/clk-provider.h>
56 /* Structure to describe features of a particular 9-series model */
74 * Renesas 9-series i2c regmap
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/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,9series.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas 9-series I2C PCIe clock generators
10 The Renesas 9-series are I2C PCIe clock generators providing
16 - 9FGV0241:
17 0 -- DIF0
18 1 -- DIF1
19 - 9FGV0441:
20 0 -- DIF0
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could
14 per-peripheral and there can be multiple peripherals attached to a
20 - Mark Brown <broonie@kernel.org>
28 - minimum: 0
33 spi-cs-high:
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/linux/fs/adfs/
H A Ddir_f.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1997-1999 Russell King
48 int _off = idx - (_buf << blocksize_bits);\
49 *(u8 *)(bh[_buf]->b_data + _off); \
54 int _off = idx - (_buf << blocksize_bits);\
55 *(__le32 *)(bh[_buf]->b_data + _off); \
60 int _off = _idx - (_buf << blocksize_bits);\
61 (void *)(_bh[_buf]->b_data + _off); \
72 struct buffer_head * const *bh = dir->bh; in adfs_dir_checkbyte()
73 const int blocksize_bits = dir->sb->s_blocksize_bits; in adfs_dir_checkbyte()
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/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
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/linux/drivers/input/touchscreen/
H A Dsun4i-ts.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2013 - 2014 Hans de Goede <hdegoede@redhat.com>
12 * The sun4i-ts controller is capable of detecting a second touch, but when a
18 * open / close movement, and then reports emulated multi-touch events around
19 * the last touch coordinate (as the dual-touch coordinates are worthless).
122 x = readl(ts->base + TP_DATA); in sun4i_ts_irq_handle_input()
123 y = readl(ts->base + TP_DATA); in sun4i_ts_irq_handle_input()
125 if (!ts->ignore_fifo_data) { in sun4i_ts_irq_handle_input()
126 input_report_abs(ts->input, ABS_X, x); in sun4i_ts_irq_handle_input()
127 input_report_abs(ts->input, ABS_Y, y); in sun4i_ts_irq_handle_input()
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/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
39 (clk_mgr_dce->regs->reg)
43 clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name
46 clk_mgr_dce->base.ctx
48 clk_mgr->ctx->logger
52 /* ClocksStateInvalid - should not be used */
54 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
64 /*ClocksStateInvalid - should not be used*/
66 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
76 /*ClocksStateInvalid - should not be used*/
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/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
187 * @steps: number of steps of SSC (Spread Spectrum Clock)
198 * struct xpsgtr_phy - representation of a lane
219 * struct xpsgtr_dev - representation of a ZynMP GT device
271 return readl(gtr_dev->serdes + reg); in xpsgtr_read()
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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
41 * since the registers are 16-bit.
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
301 /*-----------------------------------------------------------*/
392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
400 if (lane->id == 2) { in comphy_lane_reg_set()
402 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
406 void __iomem *base = lane->id == 1 ? in comphy_lane_reg_set()
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/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
11 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
184 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
364 bool spread; member
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
16 nvidia,hpd-gpio =
18 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
19 vdd-supply = <&reg_3v3_avdd_hdmi>;
24 lan-reset-n-hog {
25 gpio-hog;
27 output-high;
28 line-name = "LAN_RESET#";
33 pinctrl-names = "default";
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/linux/drivers/usb/host/
H A Duhci-hcd.c1 // SPDX-License-Identifier: GPL-2.0
8 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
10 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
11 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
15 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
16 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
17 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
40 #include <linux/dma-mapping.h>
50 #include "uhci-hcd.h"
105 * There's not much to be done about period-1 interrupts; they have in uhci_frame_skel_link()
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/linux/drivers/net/phy/
H A Ddp83td510.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
16 /* Bit 7 - mii_interrupt, active high. Clears on read.
40 * 32-bit or 16-bit counters for TX and RX statistics and must be read in
43 * - DP83TD510E_PKT_STAT_1: Contains TX packet count bits [15:0].
44 * - DP83TD510E_PKT_STAT_2: Contains TX packet count bits [31:16].
45 * - DP83TD510E_PKT_STAT_3: Contains TX error packet count.
46 * - DP83TD510E_PKT_STAT_4: Contains RX packet count bits [15:0].
47 * - DP83TD510E_PKT_STAT_5: Contains RX packet count bits [31:16].
48 * - DP83TD510E_PKT_STAT_6: Contains RX error packet count.
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/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
253 /* Exynos9 - GS101 */
387 for (; (tune)->region != PTR_INVALID; ++(tune))
441 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
449 * @hs_phy: pointer to non-Samsung IP high-speed phy controller
457 * @orientation: TypeC connector orientation - normal or flipped
487 phys[(inst)->index]); in to_usbdrd_phy()
524 return -EINVAL; in exynos5_rate_to_clk()
535 if (!inst->reg_pmu) in exynos5_usbdrd_phy_isol()
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/linux/drivers/net/wireless/ti/wl1251/
H A Dacx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 1998-2007 Texas Instruments Incorporated
70 * bits 0 - 15: Reserved.
71 * bits 16 - 23: Version ID - The WiLink version ID
73 * bits 24 - 31: Chip ID - The WiLink chip ID.
93 /* 0 - Always active*/
94 /* 1 - Power down mode: light / fast sleep*/
95 /* 2 - ELP mode: Deep / Max sleep*/
191 * 13 Copy RX Status - when set, write three receive status words
195 * 11 RX Complete upon FCS error - when set, give rx complete
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/linux/drivers/video/fbdev/
H A Dmacfb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * (c) 1999 David Huggins-Daines <dhd@debian.org>
9 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
43 /* Address for the built-in Civic framebuffer in Quadra AVs */
148 static int lastreg = -2; in dafb_setpalette()
161 nubus_writel(0, &dafb_cmap_regs->reset); in dafb_setpalette()
166 nubus_writeb(info->cmap.red[i] >> 8, in dafb_setpalette()
167 &dafb_cmap_regs->lut); in dafb_setpalette()
169 nubus_writeb(info->cmap.green[i] >> 8, in dafb_setpalette()
170 &dafb_cmap_regs->lut); in dafb_setpalette()
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/linux/Documentation/networking/
H A Dscaling.rst1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
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/linux/net/can/j1939/
H A Dsocket.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2010-2011 EIA Electronics,
4 // Copyright (c) 2010-2011 EIA Electronics,
8 // Copyright (c) 2017-2019 Pengutronix,
9 // Marc Kleine-Budde <kernel@pengutronix.de>
10 // Copyright (c) 2017-2019 Pengutronix,
11 // Oleksij Rempel <kernel@pengutronix.de>
15 #include <linux/can/can-ml.h>
21 #include "j1939-priv.h"
32 return 7 - sk_priority; in j1939_prio()
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/linux/io_uring/
H A Dio_uring.c1 // SPDX-License-Identifier: GPL-2.0
14 * through a control-dependency in io_get_cqe (smp_store_release to
39 * Copyright (C) 2018-2019 Jens Axboe
40 * Copyright (c) 2018-2019 Christoph Hellwig
80 #include "io-wq.h"
137 * so that tests against ->cq_wait_nr would fail and skip wake_up().
139 #define IO_CQ_WAKE_INIT (-1U)
140 /* Forced wake up if there is a waiter regardless of ->cq_wait_nr */
157 static int __read_mostly sysctl_io_uring_group = -1;
182 req->ctx = IO_URING_PTR_POISON; in io_poison_cached_req()
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/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
63 -------------- | +->| GATE TIMER 0 |
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/linux/fs/jffs2/
H A Dwbuf.c2 * JFFS2 -- Journalling Flash File System, Version 2.
4 * Copyright © 2001-2007 Red Hat, Inc.
5 * Copyright © 2004 Thomas Gleixner <tglx@linutronix.de>
8 * Modified debugged and enhanced by Thomas Gleixner <tglx@linutronix.de>
35 #define PAGE_DIV(x) ( ((unsigned long)(x) / (unsigned long)(c->wbuf_pagesize)) * (unsigned long)(c-…
36 #define PAGE_MOD(x) ( (unsigned long)(x) % (unsigned long)(c->wbuf_pagesize) )
50 struct jffs2_inodirty *this = c->wbuf_inodes; in jffs2_wbuf_pending_for_ino()
56 /* If ino == 0, _any_ non-GC writes mean 'yes' */ in jffs2_wbuf_pending_for_ino()
62 if (this->ino == ino) in jffs2_wbuf_pending_for_ino()
64 this = this->next; in jffs2_wbuf_pending_for_ino()
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/linux/include/linux/
H A Dsched.h1 /* SPDX-License-Identifier: GPL-2.0 */
42 #include <linux/posix-timers_types.h>
49 #include <linux/tracepoint-defs.h>
53 #include <generated/rq-offsets.h>
97 * We have two separate sets of flags: task->__state
98 * is about runnability, while task->exit_state are
104 /* Used in tsk->__state: */
110 /* Used in tsk->exit_state: */
114 /* Used in tsk->__state again: */
127 #define TASK_ANY (TASK_STATE_MAX-1)
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/linux/drivers/pci/controller/
H A Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
15 #include <linux/irqchip/irq-msi-lib.h>
27 #include <linux/pci-ecam.h>
38 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
171 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
173 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
201 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX])
202 #define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA])
203 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1])
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