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/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dclock_source.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
65 * Display Port HW De spread of Reference Clock related Parameters structure
70 /* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
87 /*> DP reference clock - calculated only for DP signal for specific cases*/
89 /*> Encoder object Id - needed by VBIOS Exec table*/
91 /*> signalType -> Encoder Mode - needed by VBIOS Exec table*/
93 /*> ControllerId - which controller using this PLL*/
96 /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
/linux/drivers/clk/
H A Dclk-renesas-pcie.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Renesas 9-series PCIe clock generator driver
6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
8 * - 9FGV0241
9 * - 9FGV0441
10 * - 9FGV0841
12 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
15 #include <linux/clk-provider.h>
56 /* Structure to describe features of a particular 9-series model */
74 * Renesas 9-series i2c regmap
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/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,9series.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas 9-series I2C PCIe clock generators
10 The Renesas 9-series are I2C PCIe clock generators providing
16 - 9FGV0241:
17 0 -- DIF0
18 1 -- DIF1
19 - 9FGV0441:
20 0 -- DIF0
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/linux/Documentation/devicetree/bindings/arm/
H A Dsyna.txt3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
18 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
19 "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
20 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
21 "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
26 model = "Sony NSZ-GS7";
27 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
38 - compatible: should be "marvell,berlin-cpu-ctrl"
39 - reg: address and length of the register set
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <broonie@kernel.org>
27 - minimum: 0
32 spi-cs-high:
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/linux/fs/adfs/
H A Ddir_f.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1997-1999 Russell King
48 int _off = idx - (_buf << blocksize_bits);\
49 *(u8 *)(bh[_buf]->b_data + _off); \
54 int _off = idx - (_buf << blocksize_bits);\
55 *(__le32 *)(bh[_buf]->b_data + _off); \
60 int _off = _idx - (_buf << blocksize_bits);\
61 (void *)(_bh[_buf]->b_data + _off); \
72 struct buffer_head * const *bh = dir->bh; in adfs_dir_checkbyte()
73 const int blocksize_bits = dir->sb->s_blocksize_bits; in adfs_dir_checkbyte()
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/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
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/linux/drivers/input/touchscreen/
H A Dsun4i-ts.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2013 - 2014 Hans de Goede <hdegoede@redhat.com>
12 * The sun4i-ts controller is capable of detecting a second touch, but when a
18 * open / close movement, and then reports emulated multi-touch events around
19 * the last touch coordinate (as the dual-touch coordinates are worthless).
122 x = readl(ts->base + TP_DATA); in sun4i_ts_irq_handle_input()
123 y = readl(ts->base + TP_DATA); in sun4i_ts_irq_handle_input()
125 if (!ts->ignore_fifo_data) { in sun4i_ts_irq_handle_input()
126 input_report_abs(ts->input, ABS_X, x); in sun4i_ts_irq_handle_input()
127 input_report_abs(ts->input, ABS_Y, y); in sun4i_ts_irq_handle_input()
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/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
39 (clk_mgr_dce->regs->reg)
43 clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name
46 clk_mgr_dce->base.ctx
48 clk_mgr->ctx->logger
52 /* ClocksStateInvalid - should not be used */
54 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
64 /*ClocksStateInvalid - should not be used*/
66 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
76 /*ClocksStateInvalid - should not be used*/
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
47 (clk_mgr->regs->reg)
51 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
68 /* ClocksStateInvalid - should not be used */
70 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
88 * (did - DENTIST_BASE_DID_1); in dentist_get_divider_from_did()
91 * (did - DENTIST_BASE_DID_2); in dentist_get_divider_from_did()
94 * (did - DENTIST_BASE_DID_3); in dentist_get_divider_from_did()
97 * (did - DENTIST_BASE_DID_4); in dentist_get_divider_from_did()
103 if clock is spread for all cases:
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/linux/Documentation/driver-api/phy/
H A Dphy.rst8 and how-to-use.
15 such as serialization, de-serialization, encoding, decoding and is responsible
21 The intention of creating this framework is to bring the PHY drivers spread
22 all over the Linux kernel to drivers/phy to increase code re-use and for
121 non-dt boot, it should contain the label of the PHY. The two
126 functions will never return -ENODEV, but instead return NULL when
197 pm_runtime_get_sync of PHY provider device because of parent-child relationship.
224 Documentation/devicetree/bindings/phy/phy-bindings.txt
/linux/drivers/gpu/drm/stm/
H A Dlvds.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
4 * Author(s): Raphaël GALLAIS-POU <raphael.gallais-pou@foss.st.com> for STMicroelectronics.
16 #include <linux/clk-provider.h>
19 #include <linux/media-bus-format.h>
62 #define CR_LK1POL GENMASK(20, 16) /* Link-1 output Polarity */
63 #define CR_LK2POL GENMASK(25, 21) /* Link-2 output Polarity */
96 #define PHY_PLLCR1_EN_SD BIT(1) /* LVDS PHY PLL sigma-delta signal enable */
120 * ,--------. ,--------. ,--------. ,--------. ,---------.
123 * `--------' `--------' `--------' `--------' `---------'
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/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 * +----+ | +----+
23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24 * +----+ | +----+
26 * | +----+ |
27 * o---| /2 |--o--|\
28 * | +----+ | \ +----+
29 * | | |--| n2 |-- dsi0pll
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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
41 * since the registers are 16-bit.
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
301 /*-----------------------------------------------------------*/
392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
400 if (lane->id == 2) { in comphy_lane_reg_set()
402 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
406 void __iomem *base = lane->id == 1 ? in comphy_lane_reg_set()
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/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
11 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
184 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
356 bool spread; member
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
16 nvidia,hpd-gpio =
18 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
19 vdd-supply = <&reg_3v3_avdd_hdmi>;
24 lan-reset-n-hog {
25 gpio-hog;
27 output-high;
28 line-name = "LAN_RESET#";
33 pinctrl-names = "default";
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/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
194 /* Exynos9 - GS101 */
324 for (; (tune)->region != PTR_INVALID; ++(tune))
378 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
415 phys[(inst)->index]); in to_usbdrd_phy()
452 return -EINVAL; in exynos5_rate_to_clk()
463 if (!inst->reg_pmu) in exynos5_usbdrd_phy_isol()
468 regmap_update_bits(inst->reg_pmu, inst->pmu_offset, in exynos5_usbdrd_phy_isol()
474 * from clock core. Further sets multiplier values and spread spectrum
[all …]
/linux/drivers/usb/host/
H A Duhci-hcd.c1 // SPDX-License-Identifier: GPL-2.0
8 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
10 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
11 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
15 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
16 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
17 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
40 #include <linux/dma-mapping.h>
50 #include "uhci-hcd.h"
105 * There's not much to be done about period-1 interrupts; they have in uhci_frame_skel_link()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_pch_refclk.c1 // SPDX-License-Identifier: MIT
20 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); in lpt_fdi_reset_mphy()
26 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); in lpt_fdi_reset_mphy()
131 p->iclk_virtual_root_freq = 172800 * 1000; in iclkip_params_init()
132 p->iclk_pi_range = 64; in iclkip_params_init()
137 return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq, in lpt_iclkip_freq()
138 p->desired_divisor << p->auxdiv); in lpt_iclkip_freq()
146 * but the adjusted_mode->crtc_clock in KHz. To get the in lpt_compute_iclkip()
151 for (p->auxdiv = 0; p->auxdiv < 2; p->auxdiv++) { in lpt_compute_iclkip()
152 p->desired_divisor = DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq, in lpt_compute_iclkip()
[all …]
/linux/drivers/md/
H A Ddm-cache-policy-smq.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include "dm-cache-background-tracker.h"
9 #include "dm-cache-policy-internal.h"
10 #include "dm-cache-policy.h"
20 #define DM_MSG_PREFIX "cache-policy-smq"
22 /*----------------------------------------------------------------*/
37 /*----------------------------------------------------------------*/
52 /*----------------------------------------------------------------*/
54 #define INDEXER_NULL ((1u << 28u) - 1u)
69 es->begin = es->end = NULL; in space_init()
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/linux/drivers/net/wireless/ti/wl1251/
H A Dacx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 1998-2007 Texas Instruments Incorporated
70 * bits 0 - 15: Reserved.
71 * bits 16 - 23: Version ID - The WiLink version ID
73 * bits 24 - 31: Chip ID - The WiLink chip ID.
93 /* 0 - Always active*/
94 /* 1 - Power down mode: light / fast sleep*/
95 /* 2 - ELP mode: Deep / Max sleep*/
191 * 13 Copy RX Status - when set, write three receive status words
195 * 11 RX Complete upon FCS error - when set, give rx complete
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/linux/Documentation/networking/
H A Dscaling.rst1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
[all …]
/linux/drivers/video/fbdev/
H A Dmacfb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * (c) 1999 David Huggins-Daines <dhd@debian.org>
9 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
43 /* Address for the built-in Civic framebuffer in Quadra AVs */
148 static int lastreg = -2; in dafb_setpalette()
161 nubus_writel(0, &dafb_cmap_regs->reset); in dafb_setpalette()
166 nubus_writeb(info->cmap.red[i] >> 8, in dafb_setpalette()
167 &dafb_cmap_regs->lut); in dafb_setpalette()
169 nubus_writeb(info->cmap.green[i] >> 8, in dafb_setpalette()
170 &dafb_cmap_regs->lut); in dafb_setpalette()
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/linux/net/can/j1939/
H A Dsocket.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2010-2011 EIA Electronics,
4 // Copyright (c) 2010-2011 EIA Electronics,
8 // Copyright (c) 2017-2019 Pengutronix,
9 // Marc Kleine-Budde <kernel@pengutronix.de>
10 // Copyright (c) 2017-2019 Pengutronix,
11 // Oleksij Rempel <kernel@pengutronix.de>
15 #include <linux/can/can-ml.h>
21 #include "j1939-priv.h"
32 return 7 - sk_priority; in j1939_prio()
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