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/linux/drivers/usb/dwc3/
H A Dep0.c30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
33 static int dwc3_ep0_delegate_req(struct dwc3 *dwc,
40 struct dwc3 *dwc; in dwc3_ep0_prepare_one_trb() local
42 dwc = dep->dwc; in dwc3_ep0_prepare_one_trb()
43 trb = &dwc->ep0_trb[dep->trb_enqueue]; in dwc3_ep0_prepare_one_trb()
68 struct dwc3 *dwc; in dwc3_ep0_start_trans() local
74 dwc = dep->dwc; in dwc3_ep0_start_trans()
77 params.param0 = upper_32_bits(dwc->ep0_trb_addr); in dwc3_ep0_start_trans()
78 params.param1 = lower_32_bits(dwc->ep0_trb_addr); in dwc3_ep0_start_trans()
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H A Dhost.c27 * @dwc: Pointer to our controller context structure
29 static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc) in dwc3_power_off_all_roothub_ports() argument
39 if (dwc->xhci_resources[0].start) { in dwc3_power_off_all_roothub_ports()
40 xhci_regs = ioremap(dwc->xhci_resources[0].start, DWC3_XHCI_REGS_END); in dwc3_power_off_all_roothub_ports()
42 dev_err(dwc->dev, "Failed to ioremap xhci_regs\n"); in dwc3_power_off_all_roothub_ports()
59 dev_err(dwc->dev, "xhci base reg invalid\n"); in dwc3_power_off_all_roothub_ports()
66 struct dwc3 *dwc; in dwc3_xhci_plat_start() local
72 dwc = dev_get_drvdata(pdev->dev.parent); in dwc3_xhci_plat_start()
74 dwc3_enable_susphy(dwc, true); in dwc3_xhci_plat_start()
81 static void dwc3_host_fill_xhci_irq_res(struct dwc3 *dwc, in dwc3_host_fill_xhci_irq_res() argument
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H A Dulpi.c24 static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr, bool read) in dwc3_ulpi_busyloop() argument
36 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); in dwc3_ulpi_busyloop()
42 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); in dwc3_ulpi_busyloop()
53 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_ulpi_read() local
58 dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); in dwc3_ulpi_read()
60 ret = dwc3_ulpi_busyloop(dwc, addr, true); in dwc3_ulpi_read()
64 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); in dwc3_ulpi_read()
71 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_ulpi_write() local
76 dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); in dwc3_ulpi_write()
78 return dwc3_ulpi_busyloop(dwc, addr, false); in dwc3_ulpi_write()
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H A Ddwc3-pci.c224 static int dwc3_pci_quirks(struct dwc3_pci *dwc, in dwc3_pci_quirks() argument
227 struct pci_dev *pdev = dwc->pci; in dwc3_pci_quirks()
233 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); in dwc3_pci_quirks()
234 dwc->has_dsm_for_pm = true; in dwc3_pci_quirks()
288 dwc->dwc3->id = PLATFORM_DEVID_NONE; in dwc3_pci_quirks()
309 return device_add_software_node(&dwc->dwc3->dev, swnode); in dwc3_pci_quirks()
315 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); in dwc3_pci_resume_work() local
316 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work()
332 struct dwc3_pci *dwc; in dwc3_pci_probe() local
345 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); in dwc3_pci_probe()
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H A Ddwc3-haps.c43 struct dwc3_haps *dwc; in dwc3_haps_probe() local
56 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); in dwc3_haps_probe()
57 if (!dwc) in dwc3_haps_probe()
60 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
61 if (!dwc->dwc3) in dwc3_haps_probe()
75 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
81 dwc->pci = pci; in dwc3_haps_probe()
82 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
84 ret = device_add_software_node(&dwc->dwc3->dev, &dwc3_haps_swnode); in dwc3_haps_probe()
88 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
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H A Dglue.h14 * @dwc: Reference to dwc3 context structure
20 struct dwc3 *dwc; member
26 void dwc3_core_remove(struct dwc3 *dwc);
28 int dwc3_runtime_suspend(struct dwc3 *dwc);
29 int dwc3_runtime_resume(struct dwc3 *dwc);
30 int dwc3_runtime_idle(struct dwc3 *dwc);
31 int dwc3_pm_suspend(struct dwc3 *dwc);
32 int dwc3_pm_resume(struct dwc3 *dwc);
33 void dwc3_pm_complete(struct dwc3 *dwc);
34 int dwc3_pm_prepare(struct dwc3 *dwc);
H A Ddwc3-generic-plat.c17 struct dwc3 dwc; member
23 #define to_dwc3_generic(d) container_of((d), struct dwc3_generic, dwc)
74 dwc3g->dwc.dev = dev; in dwc3_generic_probe()
75 probe_data.dwc = &dwc3g->dwc; in dwc3_generic_probe()
87 struct dwc3 *dwc = platform_get_drvdata(pdev); in dwc3_generic_remove() local
89 dwc3_core_remove(dwc); in dwc3_generic_remove()
94 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_generic_suspend() local
95 struct dwc3_generic *dwc3g = to_dwc3_generic(dwc); in dwc3_generic_suspend()
98 ret = dwc3_pm_suspend(dwc); in dwc3_generic_suspend()
109 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_generic_resume() local
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H A Dgadget.h110 void dwc3_ep0_interrupt(struct dwc3 *dwc,
112 void dwc3_ep0_out_start(struct dwc3 *dwc);
113 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep);
114 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc);
120 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc);
122 int dwc3_gadget_start_config(struct dwc3 *dwc, unsigned int resource_index);
141 * @dwc: pointer to our context structure
147 static inline void dwc3_gadget_dctl_write_safe(struct dwc3 *dwc, u32 value) in dwc3_gadget_dctl_write_safe() argument
150 dwc3_writel(dwc->regs, DWC3_DCTL, value); in dwc3_gadget_dctl_write_safe()
H A Ddwc3-imx8mp.c145 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_interrupt() local
153 if ((dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc->xhci) in dwc3_imx8mp_interrupt()
154 pm_runtime_resume(&dwc->xhci->dev); in dwc3_imx8mp_interrupt()
155 else if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) in dwc3_imx8mp_interrupt()
156 pm_runtime_get(dwc->dev); in dwc3_imx8mp_interrupt()
299 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_resume() local
314 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) { in dwc3_imx8mp_resume()
315 pm_runtime_mark_last_busy(dwc->dev); in dwc3_imx8mp_resume()
316 pm_runtime_put_autosuspend(dwc->dev); in dwc3_imx8mp_resume()
/linux/drivers/dma/dw/
H A Dcore.c49 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) in dwc_first_active() argument
51 return to_dw_desc(dwc->active_list.next); in dwc_first_active()
57 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); in dwc_tx_submit() local
61 spin_lock_irqsave(&dwc->lock, flags); in dwc_tx_submit()
70 list_add_tail(&desc->desc_node, &dwc->queue); in dwc_tx_submit()
71 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_tx_submit()
78 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) in dwc_desc_get() argument
80 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_get()
88 dwc->descs_allocated++; in dwc_desc_get()
90 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); in dwc_desc_get()
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H A Ddw.c14 static void dw_dma_initialize_chan(struct dw_dma_chan *dwc) in dw_dma_initialize_chan() argument
16 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dw_dma_initialize_chan()
17 u32 cfghi = is_slave_direction(dwc->direction) ? 0 : DWC_CFGH_FIFO_MODE; in dw_dma_initialize_chan()
18 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); in dw_dma_initialize_chan()
19 bool hs_polarity = dwc->dws.hs_polarity; in dw_dma_initialize_chan()
21 cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); in dw_dma_initialize_chan()
22 cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); in dw_dma_initialize_chan()
28 channel_writel(dwc, CFG_LO, cfglo); in dw_dma_initialize_chan()
29 channel_writel(dwc, CFG_HI, cfghi); in dw_dma_initialize_chan()
32 static void dw_dma_suspend_chan(struct dw_dma_chan *dwc, bool drain) in dw_dma_suspend_chan() argument
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H A Didma32.c36 static unsigned int idma32_get_slave_devfn(struct dw_dma_chan *dwc) in idma32_get_slave_devfn() argument
38 struct device *slave = dwc->chan.slave; in idma32_get_slave_devfn()
46 static void idma32_initialize_chan_xbar(struct dw_dma_chan *dwc) in idma32_initialize_chan_xbar() argument
48 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in idma32_initialize_chan_xbar()
58 value |= dwc->chan.chan_id; in idma32_initialize_chan_xbar()
63 value = readl(misc + DMA_CTL_CH(dwc->chan.chan_id)); in idma32_initialize_chan_xbar()
69 switch (dwc->direction) { in idma32_initialize_chan_xbar()
88 writel(value, misc + DMA_CTL_CH(dwc->chan.chan_id)); in idma32_initialize_chan_xbar()
91 value = readl(misc + DMA_XBAR_SEL(dwc->chan.chan_id)); in idma32_initialize_chan_xbar()
95 value |= idma32_get_slave_devfn(dwc); in idma32_initialize_chan_xbar()
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H A Dregs.h298 __dwc_regs(struct dw_dma_chan *dwc) in __dwc_regs() argument
300 return dwc->ch_regs; in __dwc_regs()
303 #define channel_readl(dwc, name) \ argument
304 readl(&(__dwc_regs(dwc)->name))
305 #define channel_writel(dwc, name, val) \ argument
306 writel((val), &(__dwc_regs(dwc)->name))
326 void (*initialize_chan)(struct dw_dma_chan *dwc);
327 void (*suspend_chan)(struct dw_dma_chan *dwc, bool drain);
328 void (*resume_chan)(struct dw_dma_chan *dwc, bool drain);
329 u32 (*prepare_ctllo)(struct dw_dma_chan *dwc);
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/linux/drivers/pwm/
H A Dpwm-dwc-core.c22 #include "pwm-dwc.h"
24 static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) in __dwc_pwm_set_enable() argument
28 reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm)); in __dwc_pwm_set_enable()
35 dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm)); in __dwc_pwm_set_enable()
38 static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, in __dwc_pwm_configure_timer() argument
52 tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); in __dwc_pwm_configure_timer()
58 dwc->clk_ns); in __dwc_pwm_configure_timer()
70 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); in __dwc_pwm_configure_timer()
78 dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm)); in __dwc_pwm_configure_timer()
79 dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm)); in __dwc_pwm_configure_timer()
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H A Dpwm-dwc.h64 static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) in dwc_pwm_readl() argument
66 return readl(dwc->base + offset); in dwc_pwm_readl()
69 static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset) in dwc_pwm_writel() argument
71 writel(value, dwc->base + offset); in dwc_pwm_writel()
/linux/drivers/net/ethernet/synopsys/
H A DMakefile6 obj-$(CONFIG_DWC_XLGMAC) += dwc-xlgmac.o
7 dwc-xlgmac-objs := dwc-xlgmac-net.o dwc-xlgmac-desc.o \
8 dwc-xlgmac-hw.o dwc-xlgmac-common.o \
9 dwc-xlgmac-ethtool.o
11 dwc-xlgmac-$(CONFIG_DWC_XLGMAC_PCI) += dwc-xlgmac-pci.o
H A DKconfig20 tristate "Synopsys DWC Enterprise Ethernet (XLGMAC) driver support"
26 Ethernet (dwc-xlgmac).
34 This selects the pci bus support for the dwc-xlgmac driver.
/linux/Documentation/devicetree/bindings/ata/
H A Dsnps,dwc-ahci.yaml4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
7 title: Synopsys DWC AHCI SATA controller
13 This document defines device tree bindings for the generic Synopsys DWC
20 - snps,dwc-ahci
26 - $ref: snps,dwc-ahci-common.yaml#
32 const: snps,dwc-ahci
38 $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
55 compatible = "snps,dwc-ahci";
H A Dsnps,dwc-ahci-common.yaml4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
7 title: Synopsys DWC AHCI SATA controller properties
13 This document defines device tree schema for the generic Synopsys DWC
30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
61 normally supported by the DWC AHCI SATA controller.
83 $ref: '#/$defs/dwc-ahci-port'
88 dwc-ahci-port:
H A Dbaikal,bt1-ahci.yaml14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
50 $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
72 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
78 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
83 - "snps,dwc-qos-ethernet-4.10" (deprecated):
97 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
99 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
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/linux/drivers/ufs/host/
H A DMakefile3 obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210.o
4 obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o
H A Dtc-dwc-g210-pltfrm.c18 #include "ufshcd-dwc.h"
19 #include "tc-dwc-g210.h"
22 * UFS DWC specific variant operations
25 .name = "tc-dwc-g210-pltfm",
31 .name = "tc-dwc-g210-pltfm",
91 .name = "tc-dwc-g210-pltfm",
99 MODULE_ALIAS("platform:tc-dwc-g210-pltfm");
/linux/Documentation/devicetree/bindings/ufs/
H A Dsnps,tc-dwc-g210.yaml4 $id: http://devicetree.org/schemas/ufs/snps,tc-dwc-g210.yaml#
18 - snps,dwc-ufshcd-1.40a
31 - const: snps,dwc-ufshcd-1.40a
47 "snps,dwc-ufshcd-1.40a",
/linux/drivers/pci/controller/dwc/
H A Dpcie-designware-ep.c21 * @ep: DWC EP device
58 * @pci: DWC PCI device
80 * @pci: DWC PCI device
270 * 32-bit Memory BAR0" in DWC EP databook 5.96a. We simply need to write in dw_pcie_ep_set_bar_resizable()
293 * Example for 32-bit Memory BAR0" in DWC EP databook 5.96a. in dw_pcie_ep_set_bar_resizable()
351 * DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs in dw_pcie_ep_set_bar()
645 * @ep: DWC EP device
663 * @ep: DWC EP device
721 * @ep: DWC EP device
748 * @ep: DWC EP device
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