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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_audio.c1079 /* calculate DTO settings */ in dce_aud_wall_dto_setup()
1093 /* On TN/SI, Program DTO source select and DTO select before in dce_aud_wall_dto_setup()
1094 programming DTO modulo and DTO phase. These bits must be in dce_aud_wall_dto_setup()
1120 calculate DTO settings */ in dce_aud_wall_dto_setup()
1126 /* Program DTO select before programming DTO modulo and DTO in dce_aud_wall_dto_setup()
1172 /* calculate DTO settings */ in dce60_aud_wall_dto_setup()
1186 /* On TN/SI, Program DTO source select and DTO select before in dce60_aud_wall_dto_setup()
1187 programming DTO modulo and DTO phase. These bits must be in dce60_aud_wall_dto_setup()
1213 calculate DTO settings */ in dce60_aud_wall_dto_setup()
1219 /* Program DTO select before programming DTO modulo and DTO in dce60_aud_wall_dto_setup()
H A Ddce_clk_mgr.c122 * (DP DTO / DP Audio DTO and DP GTC)
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
H A Ddcn32_dccg.c209 /* DTO Output Rate / Pixel Rate = 1/4 */ in dccg32_set_dtbclk_dto()
232 /* The recommended programming sequence to enable DTBCLK DTO to generate in dccg32_set_dtbclk_dto()
233 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should in dccg32_set_dtbclk_dto()
234 * be set only after DTO is enabled in dccg32_set_dtbclk_dto()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
82 * DTO should be on to divide down un-used in dccg21_update_dpp_dto()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c159 // if clock is being lowered, increase DTO before lowering refclk in dcn201_update_clocks()
163 // if clock is being raised, increase refclk before lowering DTO in dcn201_update_clocks()
/linux/drivers/infiniband/ulp/iser/
H A Diser_initiator.c44 * dto descriptor. Data size is stored in
85 * dto descriptor. Data size is stored in
355 /* build the tx desc regd header and add it to the tx desc dto */ in iser_send_command()
482 /* build the tx desc regd header and add it to the tx desc dto */ in iser_send_control()
H A Diser_verbs.c851 * iser_post_send - Initiate a Send DTO operation
/linux/drivers/gpu/drm/amd/display/include/
H A Daudio_types.h77 /* PLL information required for AZALIA DTO calculation */
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c323 // if clock is being lowered, increase DTO before lowering refclk in dcn2_update_clocks()
327 // if clock is being raised, increase refclk before lowering DTO in dcn2_update_clocks()
387 * So take the higher value since the DPP DTO is typically programmed in dcn2_update_clocks_fpga()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c303 /* if clock is being lowered, increase DTO before lowering refclk */ in dcn3_update_clocks()
307 /* if clock is being raised, increase refclk before lowering DTO */ in dcn3_update_clocks()
311 * that we do not lower dto when it is not safe to lower. We do not need to in dcn3_update_clocks()
/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml136 The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
141 Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c214 // increase per DPP DTO before lowering global dppclk with requested dppclk in rn_update_clocks()
224 //update dpp dto with actual dpp clk. in rn_update_clocks()
232 // increase global DPPCLK before lowering per DPP DTO in rn_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2962 /* DTBCLK DTO Control - 4 DTOs */
2965 uint32_t dtbclk_dto_dbuf_en; /* DTBCLK_DTO_DBUF_EN->DTBCLK DTO data buffer enable */
2969 …uint32_t dp_dto_modulo[4]; /* DP_DTO0_MODULO->DP_DTO0_MODULO from DP stream DTO prog…
2970 …uint32_t dp_dto_phase[4]; /* DP_DTO0_PHASE->DP_DTO0_PHASE from DP stream DTO progra…
2971 uint32_t dp_dto_dbuf_en; /* DP_DTO_DBUF_EN->DP DTO data buffer enable */
2989 uint32_t dpiaclk_540m_dto_modulo; /* DPIACLK_540M_DTO_MODULO->DPIA 540MHz DTO modulo */
2990 uint32_t dpiaclk_540m_dto_phase; /* DPIACLK_540M_DTO_PHASE->DPIA 540MHz DTO phase */
2991 uint32_t dpiaclk_810m_dto_modulo; /* DPIACLK_810M_DTO_MODULO->DPIA 810MHz DTO modulo */
2992 uint32_t dpiaclk_810m_dto_phase; /* DPIACLK_810M_DTO_PHASE->DPIA 810MHz DTO phase */
2993 uint32_t dpiaclk_dto_cntl; /* DPIACLK_DTO_CNTL->DPIA clock DTO control */
/linux/drivers/media/dvb-frontends/
H A Dl64781.c227 l64781_readreg (state, 0x01); /* dto. */ in apply_frontend_param()
357 l64781_readreg (state, 0x01); /* dto. */ in l64781_read_status()
H A Dves1x93.c373 ves1x93_writereg (state, 0x18, 0x80); /* dto. */ in ves1x93_read_ucblocks()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c171 /* TODO: add code for programing DP DTO, currently this is down by command table */ in dcn301_smu_set_dprefclk()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.c184 /* TODO: add code for programing DP DTO, currently this is down by command table */ in dcn31_smu_set_dprefclk()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c203 /* TODO: add code for programing DP DTO, currently this is down by command table */ in dcn314_smu_set_dprefclk()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h353 int dp_dto_source_clock_in_khz; // Used to program DP DTO with ss adjustment on DCN314
/linux/drivers/media/i2c/
H A Dsaa711x_regs.h541 "Nominal PLL2 DTO"},
/linux/net/sunrpc/xprtrdma/
H A Dsvc_rdma_transport.c575 /* Take a reference in case the DTO handler runs */ in svc_rdma_accept()
/linux/drivers/media/tuners/
H A Dtda8290.c153 { { 0x07, 0x00} }, /* use the same radio DTO values as a tda8295 */
/linux/drivers/mmc/host/
H A Dtifm_sd.c39 #define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2046 …7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2047 …PCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2048 …PCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2049 …PCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2097 …PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2098 …DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2099 …DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2100 …DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c1640 /* Step 1: Set DTO DSCCLK for main DSC if needed */ in dcn401_add_dsc_sequence_for_odm_change()
1658 /* Set DTO DSCCLK for ODM DSC if needed */ in dcn401_add_dsc_sequence_for_odm_change()
3585 /* Step 2: DCCG update DPP DTO */ in dcn401_update_dchubp_dpp_sequence()

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