| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_audio.c | 1079 /* calculate DTO settings */ in dce_aud_wall_dto_setup()
1093 /* On TN/SI, Program DTO source select and DTO select before in dce_aud_wall_dto_setup()
1094 programming DTO modulo and DTO phase. These bits must be in dce_aud_wall_dto_setup()
1120 calculate DTO settings */ in dce_aud_wall_dto_setup()
1126 /* Program DTO select before programming DTO modulo and DTO in dce_aud_wall_dto_setup()
1171 /* calculate DTO settings */ in dce60_aud_wall_dto_setup()
1185 /* On TN/SI, Program DTO source select and DTO select before in dce60_aud_wall_dto_setup()
1186 programming DTO modulo and DTO phase. These bits must be in dce60_aud_wall_dto_setup()
1212 calculate DTO settings */ in dce60_aud_wall_dto_setup()
1218 /* Program DTO select before programming DTO modulo and DTO in dce60_aud_wall_dto_setup()
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| H A D | dce_clk_mgr.c | 122 * (DP DTO / DP Audio DTO and DP GTC)
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.c | 210 /* DTO Output Rate / Pixel Rate = 1/4 */ in dccg314_set_dtbclk_dto()
233 /* The recommended programming sequence to enable DTBCLK DTO to generate in dccg314_set_dtbclk_dto()
234 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should in dccg314_set_dtbclk_dto()
235 * be set only after DTO is enabled in dccg314_set_dtbclk_dto()
340 /* turn off the DTO and leave phase/modulo at max */ in dccg314_dpp_root_clock_control()
346 /* turn on the DTO to generate a 0hz clock */ in dccg314_dpp_root_clock_control()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| H A D | dcn32_dccg.c | 209 /* DTO Output Rate / Pixel Rate = 1/4 */ in dccg32_set_dtbclk_dto()
232 /* The recommended programming sequence to enable DTBCLK DTO to generate in dccg32_set_dtbclk_dto()
233 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should in dccg32_set_dtbclk_dto()
234 * be set only after DTO is enabled in dccg32_set_dtbclk_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| H A D | dcn31_dccg.c | 52 * Do not update the DPPCLK DTO if the clock is stopped. in dccg31_update_dpp_dto()
360 //DTO must be enabled to generate a 0 Hz clock output in dccg31_disable_dscclk()
404 //Disable DTO in dccg31_enable_dscclk()
593 /* The recommended programming sequence to enable DTBCLK DTO to generate in dccg31_set_dtbclk_dto()
594 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should in dccg31_set_dtbclk_dto()
595 * be set only after DTO is enabled in dccg31_set_dtbclk_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
82 * DTO should be on to divide down un-used in dccg21_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 159 // if clock is being lowered, increase DTO before lowering refclk in dcn201_update_clocks()
163 // if clock is being raised, increase refclk before lowering DTO in dcn201_update_clocks()
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| /linux/drivers/infiniband/ulp/iser/ |
| H A D | iser_initiator.c | 44 * dto descriptor. Data size is stored in
85 * dto descriptor. Data size is stored in
355 /* build the tx desc regd header and add it to the tx desc dto */ in iser_send_command()
482 /* build the tx desc regd header and add it to the tx desc dto */ in iser_send_control()
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| H A D | iser_verbs.c | 851 * iser_post_send - Initiate a Send DTO operation
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| /linux/drivers/gpu/drm/amd/display/include/ |
| H A D | audio_types.h | 77 /* PLL information required for AZALIA DTO calculation */
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 323 // if clock is being lowered, increase DTO before lowering refclk in dcn2_update_clocks()
327 // if clock is being raised, increase refclk before lowering DTO in dcn2_update_clocks()
387 * So take the higher value since the DPP DTO is typically programmed in dcn2_update_clocks_fpga()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 303 /* if clock is being lowered, increase DTO before lowering refclk */ in dcn3_update_clocks()
307 /* if clock is being raised, increase refclk before lowering DTO */ in dcn3_update_clocks()
311 * that we do not lower dto when it is not safe to lower. We do not need to in dcn3_update_clocks()
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| /linux/Documentation/devicetree/bindings/fpga/ |
| H A D | fpga-region.yaml | 140 The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
145 Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 214 // increase per DPP DTO before lowering global dppclk with requested dppclk in rn_update_clocks()
224 //update dpp dto with actual dpp clk. in rn_update_clocks()
232 // increase global DPPCLK before lowering per DPP DTO in rn_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.c | 171 /* TODO: add code for programing DP DTO, currently this is down by command table */ in dcn301_smu_set_dprefclk()
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| /linux/drivers/media/dvb-frontends/ |
| H A D | l64781.c | 227 l64781_readreg (state, 0x01); /* dto. */ in apply_frontend_param()
357 l64781_readreg (state, 0x01); /* dto. */ in l64781_read_status()
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| H A D | ves1x93.c | 373 ves1x93_writereg (state, 0x18, 0x80); /* dto. */ in ves1x93_read_ucblocks()
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| H A D | drxk_hard.c | 2008 /* Configure DTO's */ in mpegts_dto_setup()
2012 /* Rational DTO for MCLK source (static MCLK rate), in mpegts_dto_setup()
2013 Dynamic DTO for optimal grouping in mpegts_dto_setup()
2015 DTO offset enable to sync TS burst with MSTRT */ in mpegts_dto_setup()
2026 /* Rational DTO period: in mpegts_dto_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.c | 184 /* TODO: add code for programing DP DTO, currently this is down by command table */ in dcn31_smu_set_dprefclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 203 /* TODO: add code for programing DP DTO, currently this is down by command table */ in dcn314_smu_set_dprefclk()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 353 int dp_dto_source_clock_in_khz; // Used to program DP DTO with ss adjustment on DCN314
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| /linux/drivers/mmc/host/ |
| H A D | dw_mmc.c | 2681 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) in dw_mci_read_data_pio() argument
2718 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); in dw_mci_read_data_pio()
2863 /* In case of error, we cannot expect a DTO */ in dw_mci_interrupt()
3253 * The DTO timer is much longer than the CTO timer, so it's even less in dw_mci_dto_timer()
3264 dev_warn(host->dev, "DTO timeout when already completed\n"); in dw_mci_dto_timer()
3276 * If DTO interrupt does NOT come in sending data state, in dw_mci_dto_timer()
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| H A D | omap.c | 705 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO", in mmc_omap_report_irq()
946 OMAP_MMC_WRITE(host, DTO, timeout); in set_data_timeout()
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| /linux/drivers/media/i2c/ |
| H A D | saa711x_regs.h | 541 "Nominal PLL2 DTO"},
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| /linux/drivers/media/tuners/ |
| H A D | tda8290.c | 153 { { 0x07, 0x00} }, /* use the same radio DTO values as a tda8295 */
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