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Searched full:dto (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.c211 /* DTO Output Rate / Pixel Rate = 1/4 */ in dccg314_set_dtbclk_dto()
234 /* The recommended programming sequence to enable DTBCLK DTO to generate in dccg314_set_dtbclk_dto()
235 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should in dccg314_set_dtbclk_dto()
236 * be set only after DTO is enabled in dccg314_set_dtbclk_dto()
341 /* turn off the DTO and leave phase/modulo at max */ in dccg314_dpp_root_clock_control()
347 /* turn on the DTO to generate a 0hz clock */ in dccg314_dpp_root_clock_control()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c909 /* Resync deep color DTO */ in dce110_program_pix_clk()
956 /* Resync deep color DTO */ in dce112_program_pix_clk()
989 /* Set DTO values: phase = target clock, modulo = reference clock*/ in dcn31_program_pix_clk()
993 /* Set DTO values: phase = target clock, modulo = reference clock*/ in dcn31_program_pix_clk()
997 /* Enable DTO */ in dcn31_program_pix_clk()
1057 /* Resync deep color DTO */ in dcn31_program_pix_clk()
1105 /* enable DP DTO */ in dcn401_program_pix_clk()
1114 /* disables DP DTO when provided with TMDS signal type */ in dcn401_program_pix_clk()
1160 /* Resync deep color DTO */ in dcn401_program_pix_clk()
1344 /* Set DTO values: phase = target clock, modulo = reference clock*/ in dcn3_program_pix_clk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
82 * DTO should be on to divide down un-used in dccg21_update_dpp_dto()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c159 // if clock is being lowered, increase DTO before lowering refclk in dcn201_update_clocks()
163 // if clock is being raised, increase refclk before lowering DTO in dcn201_update_clocks()
/linux/drivers/infiniband/ulp/iser/
H A Diser_initiator.c44 * dto descriptor. Data size is stored in
85 * dto descriptor. Data size is stored in
354 /* build the tx desc regd header and add it to the tx desc dto */ in iser_send_command()
481 /* build the tx desc regd header and add it to the tx desc dto */ in iser_send_control()
H A Diser_verbs.c851 * iser_post_send - Initiate a Send DTO operation
/linux/drivers/gpu/drm/amd/display/include/
H A Daudio_types.h77 /* PLL information required for AZALIA DTO calculation */
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c323 // if clock is being lowered, increase DTO before lowering refclk in dcn2_update_clocks()
327 // if clock is being raised, increase refclk before lowering DTO in dcn2_update_clocks()
387 * So take the higher value since the DPP DTO is typically programmed in dcn2_update_clocks_fpga()
/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml136 The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
141 Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h3094 /* DTBCLK DTO Control - 4 DTOs */
3097 uint32_t dtbclk_dto_dbuf_en; /* DTBCLK_DTO_DBUF_EN->DTBCLK DTO data buffer enable */
3101 …uint32_t dp_dto_modulo[4]; /* DP_DTO0_MODULO->DP_DTO0_MODULO from DP stream DTO prog…
3102 …uint32_t dp_dto_phase[4]; /* DP_DTO0_PHASE->DP_DTO0_PHASE from DP stream DTO progra…
3103 uint32_t dp_dto_dbuf_en; /* DP_DTO_DBUF_EN->DP DTO data buffer enable */
3121 uint32_t dpiaclk_540m_dto_modulo; /* DPIACLK_540M_DTO_MODULO->DPIA 540MHz DTO modulo */
3122 uint32_t dpiaclk_540m_dto_phase; /* DPIACLK_540M_DTO_PHASE->DPIA 540MHz DTO phase */
3123 uint32_t dpiaclk_810m_dto_modulo; /* DPIACLK_810M_DTO_MODULO->DPIA 810MHz DTO modulo */
3124 uint32_t dpiaclk_810m_dto_phase; /* DPIACLK_810M_DTO_PHASE->DPIA 810MHz DTO phase */
3125 uint32_t dpiaclk_dto_cntl; /* DPIACLK_DTO_CNTL->DPIA clock DTO control */
/linux/drivers/media/dvb-frontends/
H A Dl64781.c227 l64781_readreg (state, 0x01); /* dto. */ in apply_frontend_param()
357 l64781_readreg (state, 0x01); /* dto. */ in l64781_read_status()
H A Dves1x93.c373 ves1x93_writereg (state, 0x18, 0x80); /* dto. */ in ves1x93_read_ucblocks()
H A Ddrxk_hard.c2008 /* Configure DTO's */ in mpegts_dto_setup()
2012 /* Rational DTO for MCLK source (static MCLK rate), in mpegts_dto_setup()
2013 Dynamic DTO for optimal grouping in mpegts_dto_setup()
2015 DTO offset enable to sync TS burst with MSTRT */ in mpegts_dto_setup()
2026 /* Rational DTO period: in mpegts_dto_setup()
H A Ddrxd_hard.c2443 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */ in CDRXD()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c171 /* TODO: add code for programing DP DTO, currently this is down by command table */ in dcn301_smu_set_dprefclk()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.c184 /* TODO: add code for programing DP DTO, currently this is down by command table */ in dcn31_smu_set_dprefclk()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c203 /* TODO: add code for programing DP DTO, currently this is down by command table */ in dcn314_smu_set_dprefclk()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/
H A Ddcn42_clk_mgr.c342 // increase per DPP DTO before lowering global dppclk in dcn42_update_clocks()
346 // increase global DPPCLK before lowering per DPP DTO in dcn42_update_clocks()
819 * So take the higher value since the DPP DTO is typically programmed in dcn42_update_clocks_fpga()
/linux/drivers/media/i2c/
H A Dsaa711x_regs.h541 "Nominal PLL2 DTO"},
/linux/net/sunrpc/xprtrdma/
H A Dsvc_rdma_transport.c583 /* Take a reference in case the DTO handler runs */ in svc_rdma_accept()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c2472 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, in dce110_setup_audio_dto()
2473 * find first available pipe with audio, setup audio wall DTO per topology in dce110_setup_audio_dto()
3421 /* If the current pixel clock source is not DTO(happens after in dce110_enable_dp_link_output()
3423 * switch the pixel clock source to DTO. in dce110_enable_dp_link_output()
/linux/drivers/media/tuners/
H A Dtda8290.c153 { { 0x07, 0x00} }, /* use the same radio DTO values as a tda8295 */
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2046 …7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2047 …PCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2048 …PCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2049 …PCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2097 …PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2098 …DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2099 …DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2100 …DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c1565 /* Step 1: Set DTO DSCCLK for main DSC if needed */ in dcn401_add_dsc_sequence_for_odm_change()
1583 /* Set DTO DSCCLK for ODM DSC if needed */ in dcn401_add_dsc_sequence_for_odm_change()
3534 /* Step 2: DCCG update DPP DTO */ in dcn401_update_dchubp_dpp_sequence()
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c680 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings in link_set_dsc_on_stream()