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/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/video/omap2/dss/dsi.c
9 #define DSS_SUBSYS_NAME "DSI"
47 /* DSI Protocol Engine */
213 /* DSI PLL HSDIV indices */
408 return to_platform_device(dssdev->dev); in dsi_get_dsidev_from_dssdev()
429 return out ? to_platform_device(out->dev) : NULL; in dsi_get_dsidev_from_id()
435 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); in dsi_write_reg() local
439 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
440 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
24 dispc, dsi, hdmi and rfbi.
34 <debugfs>/omapdss/dsi_irq for DSI interrupts.
46 OMAP Video Encoder support for S-Video and composite TV-out.
71 SDI is a high speed one-way display serial bus between the host
75 bool "DSI support"
77 MIPI DSI (Display Serial Interface) support.
79 DSI is a high speed half-duplex serial interface between the host
82 See https://www.mipi.org/ for DSI specifications.
89 This can be used to adjust the minimum FCK/PCK ratio.
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-samsung-s6e63m0-dsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * DSI interface to the Samsung S6E63M0 panel.
14 #include "panel-samsung-s6e63m0.h"
22 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in s6e63m0_dsi_dcs_read() local
25 ret = mipi_dsi_dcs_read(dsi, cmd, data, 1); in s6e63m0_dsi_dcs_read()
27 dev_err(dev, "could not read DCS CMD %02x\n", cmd); in s6e63m0_dsi_dcs_read()
31 dev_dbg(dev, "DSI read CMD %02x = %02x\n", cmd, *data); in s6e63m0_dsi_dcs_read()
39 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in s6e63m0_dsi_dcs_write() local
47 dev_dbg(dev, "DSI writing dcs seq: %*ph\n", (int)len, data); in s6e63m0_dsi_dcs_write()
53 remain = len - 1; in s6e63m0_dsi_dcs_write()
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H A Dpanel-sharp-lq101r1sx01.c1 // SPDX-License-Identifier: GPL-2.0-only
21 /* the datasheet refers to them as DSI-LINK1 and DSI-LINK2 */
37 unsigned int refresh = drm_mode_vrefresh(sharp->mode); in sharp_wait_frames()
48 struct mipi_dsi_device *dsi = sharp->link1; in sharp_panel_write() local
51 err = mipi_dsi_generic_write(dsi, payload, sizeof(payload)); in sharp_panel_write()
53 dev_err(&dsi->dev, "failed to write %02x to %04x: %zd\n", in sharp_panel_write()
58 err = mipi_dsi_dcs_nop(dsi); in sharp_panel_write()
60 dev_err(&dsi->dev, "failed to send DCS nop: %zd\n", err); in sharp_panel_write()
76 err = mipi_dsi_generic_read(sharp->link1, &offset, sizeof(offset), in sharp_panel_read()
79 dev_err(&sharp->link1->dev, "failed to read from %04x: %zd\n", in sharp_panel_read()
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H A Dpanel-raspberrypi-touchscreen.c2 * Copyright © 2016-2017 Broadcom
8 * Portions of this file (derived from panel-simple.c) are:
12 * Permission is hereby granted, free of charge, to any person obtaining a
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sub license,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
36 * TC358762XBG DSI-DPI bridge, and an I2C-connected Atmel ATTINY88-MUR
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H A Dpanel-truly-nt35597.c1 // SPDX-License-Identifier: GPL-2.0
64 struct mipi_dsi_device *dsi[2]; member
228 for (i = 0; i < ARRAY_SIZE(ctx->dsi); i++) { in truly_dcs_write()
229 ret = mipi_dsi_dcs_write(ctx->dsi[i], command, NULL, 0); in truly_dcs_write()
231 dev_err(ctx->dev, "cmd 0x%x failed for dsi = %d\n", command, i); in truly_dcs_write()
245 for (i = 0; i < ARRAY_SIZE(ctx->dsi); i++) { in truly_dcs_write_buf()
246 ret = mipi_dsi_dcs_write_buffer(ctx->dsi[i], buf, size); in truly_dcs_write_buf()
248 dev_err(ctx->dev, "failed to tx cmd [%d], err: %d\n", i, ret); in truly_dcs_write_buf()
260 for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++) { in truly_35597_power_on()
261 ret = regulator_set_load(ctx->supplies[i].consumer, in truly_35597_power_on()
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/linux/drivers/video/fbdev/omap2/omapfb/displays/
H A Dpanel-dsi-cm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic DSI Command Mode panel driver
28 /* DSI Virtual channel. Hardcoded for now. */
92 ddata->hw_guard_wait = msecs_to_jiffies(guard_msec); in hw_guard_start()
93 ddata->hw_guard_end = jiffies + ddata->hw_guard_wait; in hw_guard_start()
98 unsigned long wait = ddata->hw_guard_end - jiffies; in hw_guard_wait()
100 if ((long)wait > 0 && time_before_eq(wait, ddata->hw_guard_wait)) { in hw_guard_wait()
108 struct omap_dss_device *in = ddata->in; in dsicm_dcs_read_1()
112 r = in->ops.dsi->dcs_read(in, ddata->channel, dcs_cmd, buf, 1); in dsicm_dcs_read_1()
124 struct omap_dss_device *in = ddata->in; in dsicm_dcs_write_0()
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
238 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) in mtk_dsi_mask() argument
240 u32 temp = readl(dsi->regs + offset); in mtk_dsi_mask()
242 writel((temp & ~mask) | (data & mask), dsi->regs + offset); in mtk_dsi_mask()
245 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) in mtk_dsi_phy_timconfig() argument
248 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ); in mtk_dsi_phy_timconfig()
249 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig()
251 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; in mtk_dsi_phy_timconfig()
252 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; in mtk_dsi_phy_timconfig()
253 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - in mtk_dsi_phy_timconfig()
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/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9211.c1 // SPDX-License-Identifier: GPL-2.0
6 * 2xDSI/2xLVDS/1xDPI -> 2xDSI/2xLVDS/1xDPI
8 * 1xDSI -> 1xLVDS
17 #include <linux/media-bus-format.h>
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
47 struct mipi_dsi_device *dsi; member
107 return drm_bridge_attach(encoder, ctx->panel_bridge, in lt9211_attach()
108 &ctx->bridge, flags); in lt9211_attach()
117 ret = regmap_bulk_read(ctx->regmap, REG_CHIPID0, chipid, 3); in lt9211_read_chipid()
119 dev_err(ctx->dev, "Failed to read Chip ID: %d\n", ret); in lt9211_read_chipid()
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H A Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
76 /* DSI layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
78 #define DSI_BUSYDSI 0x0208 /* DSI busy status */
82 /* Lane enable PPI and DSI register bits */
89 #define DSI_LANESTATUS0 0x0214 /* DSI lane status 0 */
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H A Dlontium-lt9611uxc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2019-2020. Linaro Limited.
20 #include <sound/hdmi-codec.h>
41 /* Protects all accesses to registers by stopping the on-chip MCU */
98 * Enumerate them here to check whether the mode is supported.
126 mutex_lock(&lt9611uxc->ocm_lock); in lt9611uxc_lock()
127 regmap_write(lt9611uxc->regmap, 0x80ee, 0x01); in lt9611uxc_lock()
132 regmap_write(lt9611uxc->regmap, 0x80ee, 0x00); in lt9611uxc_unlock()
134 mutex_unlock(&lt9611uxc->ocm_lock); in lt9611uxc_unlock()
145 regmap_read(lt9611uxc->regmap, 0xb022, &irq_status); in lt9611uxc_irq_thread_handler()
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H A Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
38 #define SN_DEVICE_ID_REGS 0x00 /* up to 0x07 */
43 #define REFCLK_FREQ(x) ((x) << 1) argument
48 #define CHA_DSI_LANES(x) ((x) << 3) argument
81 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) argument
89 #define AUX_CMD_REQ(x) ((x) << 4) argument
90 #define SN_AUX_RDATA_REG(x) (0x79 + (x)) argument
93 #define DP_NUM_LANES(x) ((x) << 4) argument
96 #define DP_DATARATE(x) ((x) << 5) argument
116 /* fudge factor required to account for 8b/10b encoding */
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H A Dlontium-lt9611.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2019-2020. Linaro Limited.
10 #include <linux/media-bus-format.h>
17 #include <sound/hdmi-codec.h>
104 { 0x811c, 0x03 }, /* PortA clk lane no-LP mode */ in lt9611_mipi_input_analog()
105 { 0x8120, 0x03 }, /* PortB clk lane with-LP mode */ in lt9611_mipi_input_analog()
108 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_analog()
123 if (lt9611->dsi1_node) in lt9611_mipi_input_digital()
126 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_digital()
135 h_total = mode->htotal; in lt9611_mipi_video_setup()
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
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/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_7nm.c2 * SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <linux/clk-provider.h>
13 #include "dsi.xml.h"
17 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
22 * +---------+ | +----------+ | +----+
23 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
24 * +---------+ | +----------+ | +----+
28 * | | +----+ | |\ dsi0_pclk_mux
29 * | |--| /2 |--o--| \ |
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/linux/drivers/gpu/drm/omapdrm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 dispc, dsi, hdmi and rfbi.
46 <debugfs>/omapdss/dsi_irq for DSI interrupts.
58 OMAP Video Encoder support for S-Video and composite TV-out.
93 SDI is a high speed one-way display serial bus between the host
97 bool "DSI support"
101 MIPI DSI (Display Serial Interface) support.
103 DSI is a high speed half-duplex serial interface between the host
106 See http://www.mipi.org/ for DSI specifications.
113 This can be used to adjust the minimum FCK/PCK ratio.
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_kms.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
13 #include <linux/dma-buf.h>
44 * To enable overall DRM driver logging
47 * To enable DRM driver h/w logging
66 struct dpu_kms *kms = s->private; in _dpu_danger_signal_status()
69 if (!kms->hw_mdp) { in _dpu_danger_signal_status()
76 pm_runtime_get_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
79 if (kms->hw_mdp->ops.get_danger_status) in _dpu_danger_signal_status()
[all …]
/linux/drivers/gpu/drm/kmb/
H A Dkmb_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2018-2020 Intel Corporation
34 ret = clk_prepare_enable(kmb->kmb_clk.clk_lcd); in kmb_display_clk_enable()
36 drm_err(&kmb->drm, "Failed to enable LCD clock: %d\n", ret); in kmb_display_clk_enable()
48 kmb->kmb_clk.clk_lcd = devm_clk_get(dev, "clk_lcd"); in kmb_initialize_clocks()
49 if (IS_ERR(kmb->kmb_clk.clk_lcd)) { in kmb_initialize_clocks()
50 drm_err(&kmb->drm, "clk_get() failed clk_lcd\n"); in kmb_initialize_clocks()
51 return PTR_ERR(kmb->kmb_clk.clk_lcd); in kmb_initialize_clocks()
54 kmb->kmb_clk.clk_pll0 = devm_clk_get(dev, "clk_pll0"); in kmb_initialize_clocks()
55 if (IS_ERR(kmb->kmb_clk.clk_pll0)) { in kmb_initialize_clocks()
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_drv.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 * DOC: ST-Ericsson MCDE Driver
11 * The MCDE (short for multi-channel display engine) is a graphics
15 * ST-Ericsson U8500 where is was used for mass-market deployments
18 * It can do 1080p30 on SDTV CCIR656, DPI-2, DBI-2 or DSI for
25 * Memory -> Overlay -> Channel -> FIFO -> 8 formatters -> DSI/DPI
26 * External 0..5 0..3 A,B, 6 x DSI bridge
27 * source 0..9 C0,C1 2 x DPI
31 * 6 of the formatters are for DSI, 3 pairs for VID/CMD respectively.
[all …]
H A Dmcde_display.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 #include <linux/dma-buf.h>
11 #include <linux/media-bus-format.h>
80 mispp = readl(mcde->regs + MCDE_MISPP); in mcde_display_irq()
81 misovl = readl(mcde->regs + MCDE_MISOVL); in mcde_display_irq()
82 mischnl = readl(mcde->regs + MCDE_MISCHNL); in mcde_display_irq()
85 * Handle IRQs from the DSI link. All IRQs from the DSI links in mcde_display_irq()
86 * are just latched onto the MCDE IRQ line, so we need to traverse in mcde_display_irq()
87 * any active DSI masters and check if an IRQ is originating from in mcde_display_irq()
[all …]
/linux/drivers/gpu/drm/stm/
H A Ddw_mipi_dsi-stm.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
28 /* DSI digital registers & bit definitions */
32 /* DSI wrapper registers & bit definitions */
35 #define WCFGR_DSIM BIT(0) /* DSI Mode */
39 #define WCR_DSIEN BIT(3) /* DSI ENable */
46 #define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */
63 /* dsi color format coding according to the datasheet */
86 struct dw_mipi_dsi *dsi; member
94 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) in dsi_write() argument
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/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 #define DRIVER_NAME "meson-dw-mipi-dsi"
34 #define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
51 #define encoder_to_meson_dw_mipi_dsi(x) \ argument
52 container_of(x, struct meson_dw_mipi_dsi, encoder)
61 mipi_dsi->base + MIPI_DSI_TOP_SW_RESET); in meson_dw_mipi_dsi_hw_init()
64 0, mipi_dsi->base + MIPI_DSI_TOP_SW_RESET); in meson_dw_mipi_dsi_hw_init()
69 mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL); in meson_dw_mipi_dsi_hw_init()
72 writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD); in meson_dw_mipi_dsi_hw_init()
81 /* Set the bit clock rate to hs_clk_rate */ in dw_mipi_dsi_phy_init()
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
43 * internal firmware(OCM), to avoid the race condition, AP should access
50 struct device *dev = &client->dev; in i2c_access_workaround()
53 if (client == ctx->last_client) in i2c_access_workaround()
56 ctx->last_client = client; in i2c_access_workaround()
58 if (client == ctx->i2c.tcpc_client) in i2c_access_workaround()
60 else if (client == ctx->i2c.tx_p0_client) in i2c_access_workaround()
62 else if (client == ctx->i2c.tx_p1_client) in i2c_access_workaround()
[all …]
/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_kms.h1 /* SPDX-License-Identifier: GPL-2.0-only */
60 * lock to protect access to global resources: ie., following register:
61 * - REG_MDP5_DISP_INTF_SEL
71 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base) argument
76 #define to_mdp5_global_state(x) container_of(x, struct mdp5_global_state, base) argument
91 /* Atomic plane state. Subclasses the base drm_plane_state in order to
103 /* whether attached CRTC needs pixel data explicitly flushed to
104 * display (ex. DSI command mode display)
108 #define to_mdp5_plane_state(x) \ argument
109 container_of(x, struct mdp5_plane_state, base)
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/linux/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
200 #define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */ argument
205 #define CFG_DMA_HPXL(x) (x) argument
210 #define CFG_DZM_HPXL(x) (x) argument
222 #define CFG_GRA_OVSA_HPXL(x) (x) argument
227 #define CFG_GRA_HPXL(x) (x) argument
232 #define CFG_GZM_HPXL(x) (x) argument
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