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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sc8280xp-mdss.yaml104 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
112 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm6125-mdss.yaml122 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
131 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm6375-mdss.yaml116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
126 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm6350-mdss.yaml125 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
H A Dqcom,sm8350-mdss.yaml133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
141 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm8250-mdss.yaml133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
136 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm8550-mdss.yaml129 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
137 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm8150-mdss.yaml130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
133 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
/linux/drivers/clk/qcom/
H A Ddispcc-sm6375.c461 static struct clk_branch disp_cc_mdss_vsync_clk = { variable
468 .name = "disp_cc_mdss_vsync_clk",
536 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
H A Ddispcc-sm6125.c577 static struct clk_branch disp_cc_mdss_vsync_clk = { variable
584 .name = "disp_cc_mdss_vsync_clk",
643 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
H A Ddispcc-sc7180.c608 static struct clk_branch disp_cc_mdss_vsync_clk = { variable
615 .name = "disp_cc_mdss_vsync_clk",
671 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
H A Ddispcc-sm4450.c632 static struct clk_branch disp_cc_mdss_vsync_clk = { variable
639 .name = "disp_cc_mdss_vsync_clk",
698 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
H A Ddispcc-sc7280.c757 static struct clk_branch disp_cc_mdss_vsync_clk = { variable
764 .name = "disp_cc_mdss_vsync_clk",
839 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
/linux/include/dt-bindings/clock/
H A Dqcom,sm6115-dispcc.h28 #define DISP_CC_MDSS_VSYNC_CLK 18 macro
H A Dqcom,dispcc-qcm2290.h25 #define DISP_CC_MDSS_VSYNC_CLK 15 macro
H A Dqcom,sm6375-dispcc.h30 #define DISP_CC_MDSS_VSYNC_CLK 19 macro
H A Dqcom,dispcc-sm6125.h34 #define DISP_CC_MDSS_VSYNC_CLK 25 macro
H A Dqcom,dispcc-sc7180.h39 #define DISP_CC_MDSS_VSYNC_CLK 30 macro
H A Dqcom,dispcc-sm6350.h40 #define DISP_CC_MDSS_VSYNC_CLK 29 macro
H A Dqcom,sm4450-dispcc.h33 #define DISP_CC_MDSS_VSYNC_CLK 23 macro
H A Dqcom,dispcc-sc7280.h47 #define DISP_CC_MDSS_VSYNC_CLK 37 macro
H A Dqcom,dispcc-sdm845.h33 #define DISP_CC_MDSS_VSYNC_CLK 23 macro
H A Dqcom,dispcc-sm8350.h54 #define DISP_CC_MDSS_VSYNC_CLK 44 macro
H A Dqcom,dispcc-sm8250.h54 #define DISP_CC_MDSS_VSYNC_CLK 44 macro
H A Dqcom,dispcc-sm8150.h54 #define DISP_CC_MDSS_VSYNC_CLK 44 macro

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