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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Ddpu.txt84 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
87 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
112 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
116 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
H A Dqcom,sm6350-mdss.yaml102 <&dispcc DISP_CC_MDSS_MDP_CLK>;
124 <&dispcc DISP_CC_MDSS_MDP_CLK>,
129 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
H A Dqcom,sc8280xp-dpu.yaml69 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
78 assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
H A Dqcom,sc8280xp-mdss.yaml72 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
103 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
H A Ddpu-sdm845.yaml169 <&dispcc DISP_CC_MDSS_MDP_CLK>;
188 <&dispcc DISP_CC_MDSS_MDP_CLK>,
H A Dqcom,qcm2290-mdss.yaml98 <&dispcc DISP_CC_MDSS_MDP_CLK>;
122 <&dispcc DISP_CC_MDSS_MDP_CLK>,
H A Dqcom,sm6115-mdss.yaml95 <&dispcc DISP_CC_MDSS_MDP_CLK>;
113 <&dispcc DISP_CC_MDSS_MDP_CLK>,
H A Ddpu-qcm2290.yaml176 <&dispcc DISP_CC_MDSS_MDP_CLK>;
198 <&dispcc DISP_CC_MDSS_MDP_CLK>,
H A Ddpu-sc7180.yaml181 <&dispcc DISP_CC_MDSS_MDP_CLK>;
205 <&dispcc DISP_CC_MDSS_MDP_CLK>,
H A Ddpu-sc7280.yaml179 <&dispcc DISP_CC_MDSS_MDP_CLK>;
205 <&dispcc DISP_CC_MDSS_MDP_CLK>,
H A Dqcom,sm6375-mdss.yaml93 <&dispcc DISP_CC_MDSS_MDP_CLK>;
115 <&dispcc DISP_CC_MDSS_MDP_CLK>,
H A Dqcom,sm8350-mdss.yaml109 <&dispcc DISP_CC_MDSS_MDP_CLK>;
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
H A Dqcom,sdm845-mdss.yaml99 <&dispcc DISP_CC_MDSS_MDP_CLK>;
119 <&dispcc DISP_CC_MDSS_MDP_CLK>,
H A Dqcom,sc7180-mdss.yaml106 <&dispcc DISP_CC_MDSS_MDP_CLK>;
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dqcom,dispcc-qcm2290.h19 #define DISP_CC_MDSS_MDP_CLK 9 macro
H A Dqcom,sm6115-dispcc.h20 #define DISP_CC_MDSS_MDP_CLK 10 macro
H A Dqcom,dispcc-sm6125.h26 #define DISP_CC_MDSS_MDP_CLK 17 macro
H A Dqcom,sm6375-dispcc.h20 #define DISP_CC_MDSS_MDP_CLK 9 macro
H A Dqcom,dispcc-sc7180.h29 #define DISP_CC_MDSS_MDP_CLK 20 macro
H A Dqcom,dispcc-sm6350.h30 #define DISP_CC_MDSS_MDP_CLK 19 macro
H A Dqcom,sm4450-dispcc.h20 #define DISP_CC_MDSS_MDP_CLK 10 macro
H A Dqcom,dispcc-sc7280.h37 #define DISP_CC_MDSS_MDP_CLK 27 macro
H A Dqcom,dispcc-sdm845.h22 #define DISP_CC_MDSS_MDP_CLK 12 macro
H A Dqcom,dispcc-sm8150.h42 #define DISP_CC_MDSS_MDP_CLK 32 macro
H A Dqcom,dispcc-sm8250.h42 #define DISP_CC_MDSS_MDP_CLK 32 macro

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