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Searched full:disp_cc_mdss_core_bcr (Results 1 – 24 of 24) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dqcom,dispcc-qcm2290.h36 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm6375-dispcc.h36 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm4450-dispcc.h47 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8350.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8250.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8150.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,x1e80100-dispcc.h90 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8550-dispcc.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8450-dispcc.h95 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sc8280xp.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sc8280xp-mdss.yaml77 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
H A Dqcom,sm8350-mdss.yaml104 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dqcom,sm8550-mdss.yaml98 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dqcom,sm8450-mdss.yaml101 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
/linux/drivers/clk/qcom/
H A Ddispcc-sm6375.c544 [DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
H A Ddispcc-sm4450.c712 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
H A Ddispcc-sm8250.c1220 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
H A Ddispcc-x1e80100.c1620 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
H A Ddispcc-sm8450.c1765 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
H A Ddispcc-sm8550.c1731 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
H A Ddispcc-sm8750.c1870 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
H A Ddispcc-sc8280xp.c3047 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
/linux/arch/arm64/boot/dts/qcom/
H A Dqcm2290.dtsi1597 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dx1e80100.dtsi5123 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;