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Searched full:disp_cc_mdss_core_bcr (Results 1 – 23 of 23) sorted by relevance

/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dqcom,dispcc-qcm2290.h36 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm6375-dispcc.h36 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm4450-dispcc.h47 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8150.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8250.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8350.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,x1e80100-dispcc.h90 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sc8280xp.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8450-dispcc.h95 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8550-dispcc.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8650-dispcc.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dqcom,sc8280xp-mdss.yaml77 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
H A Dqcom,sm8350-mdss.yaml104 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dqcom,sm8450-mdss.yaml101 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dqcom,sm8550-mdss.yaml98 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dqcm2290.dtsi1597 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dsc8280xp.dtsi4107 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
5394 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
H A Dsc8180x.dtsi2946 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dsm8350.dtsi2507 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dsm8650.dtsi3455 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dsm8450.dtsi3063 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dsm8550.dtsi2870 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dx1e80100.dtsi4450 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;