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/linux/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/
H A Duncore-ddrc.json5 "BriefDescription": "DDRC total write operations",
6 "Unit": "hisi_sccl,ddrc"
11 "BriefDescription": "DDRC total read operations",
12 "Unit": "hisi_sccl,ddrc"
17 "BriefDescription": "DDRC write commands",
18 "Unit": "hisi_sccl,ddrc"
23 "BriefDescription": "DDRC read commands",
24 "Unit": "hisi_sccl,ddrc"
29 "BriefDescription": "DDRC precharge commands",
30 "Unit": "hisi_sccl,ddrc"
[all …]
H A Duncore-hha.json47 "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
53 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
59 … "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
65 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dimx8m-ddrc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
20 The Linux driver for the DDRC doesn't even map registers (they're included
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
31 - const: fsl,imx8m-ddrc
36 Base address and size of DDRC CTL area.
37 This is not currently mapped by the imx8m-ddrc driver.
64 ddrc: memory-controller@3d400000 {
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dsnps,dw-umctl2-ddrc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
28 const: snps,ddrc-3.80a
30 const: snps,dw-umctl2-ddrc
32 const: xlnx,zynqmp-ddrc-2.40a
36 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
61 reference clock, DDRC core clock, Scrubber standalone clock
62 (synchronous to the DDRC clock).
96 compatible = "xlnx,zynqmp-ddrc-2.40a";
107 compatible = "snps,dw-umctl2-ddrc";
H A Dxlnx,zynq-ddrc-a05.yaml4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
20 const: xlnx,zynq-ddrc-a05
34 compatible = "xlnx,zynq-ddrc-a05";
/linux/Documentation/devicetree/bindings/interconnect/
H A Dfsl,imx8m-noc.yaml53 fsl,ddrc:
81 fsl,ddrc = <&ddrc>;
96 ddrc: memory-controller@3d400000 {
97 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_ddrc_pmu.c3 * HiSilicon SoC DDRC uncore Hardware event counters support
21 /* DDRC register definition in v1 */
37 /* DDRC register definition in v2 */
46 /* DDRC interrupt registers definition in v3 */
51 /* DDRC has 8-counters */
109 * For DDRC PMU v1, event has been mapped to fixed-purpose counter by hardware,
129 /* For DDRC PMU, we use event code as counter index */ in hisi_ddrc_pmu_v1_get_event_idx()
236 * Use the SCCL_ID and DDRC channel ID to identify the in hisi_ddrc_pmu_init_data()
237 * DDRC PMU, while SCCL_ID is in MPIDR[aff2]. in hisi_ddrc_pmu_init_data()
241 dev_err(&pdev->dev, "Can not read ddrc channel-id!\n"); in hisi_ddrc_pmu_init_data()
[all …]
H A Dhisi_uncore_pmu.h96 * @sub_id: submodule ID of the PMU. For example we use this for DDRC PMU v2
97 * since each DDRC has more than one DMC
/linux/tools/perf/pmu-events/arch/test/test_soc/cpu/
H A Duncore.json5 "BriefDescription": "DDRC write commands",
6 "PublicDescription": "DDRC write commands",
7 "Unit": "hisi_sccl,ddrc"
/linux/arch/arm/mach-zynq/
H A Dpm.c58 ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05"); in zynq_pm_late_init()
60 pr_warn("%s: Unable to map DDRC IO memory.\n", __func__); in zynq_pm_late_init()
63 * Enable DDRC clock stop feature. The HW takes care of in zynq_pm_late_init()
/linux/Documentation/admin-guide/perf/
H A Dhisi-pmu.rst6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
20 HHA and DDRC etc. The available events and configuration options shall
23 /sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>
27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
137 /sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}_{Z}/ddrc{Y}_{Z}/noc{Y}_{Z}>
H A Dalibaba_pmu.rst28 based on DDRC core clock.
53 By counting the READ, WRITE and RMW commands sent to the DDRC through the HIF
/linux/drivers/power/reset/
H A Dat91-sama5d2_shdwc.c89 struct ddrc_reg_config ddrc; member
271 .ddrc = {
288 .ddrc = {
388 if (at91_shdwc->rcfg->ddrc.type_mask) { in at91_shdwc_probe()
405 at91_shdwc->rcfg->ddrc.type_offset) & in at91_shdwc_probe()
406 at91_shdwc->rcfg->ddrc.type_mask; in at91_shdwc_probe()
/linux/drivers/devfreq/
H A Dimx8m-ddrc.c262 dev_err(dev, "ddrc failed freq switch to %lu from %lu: error %d. now at %lu\n", in imx8m_ddrc_target()
265 dev_err(dev, "ddrc failed freq update to %lu from %lu, now at %lu\n", in imx8m_ddrc_target()
268 dev_dbg(dev, "ddrc freq set to %lu (was %lu)\n", in imx8m_ddrc_target()
441 { .compatible = "fsl,imx8m-ddrc", },
449 .name = "imx8m-ddrc-devfreq",
H A DMakefile14 obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
H A DKconfig113 tristate "i.MX8M DDRC DEVFREQ Driver"
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-evk.dts20 &ddrc {
H A Dimx8mn-ddr4-evk.dts32 &ddrc {
H A Dimx8mm-kontron-sl.dtsi43 &ddrc {
/linux/drivers/edac/
H A Dsynopsys_edac.c200 /* DDRC Software control register */
203 /* DDRC ECC CE & UE poison mask */
207 /* DDRC Device config masks */
967 .compatible = "xlnx,zynq-ddrc-a05",
971 .compatible = "xlnx,zynqmp-ddrc-2.40a",
975 .compatible = "snps,ddrc-3.80a",
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_n5x_socdk.dts30 compatible = "snps,ddrc-3.80a";
/linux/arch/mips/include/asm/mach-rc32434/
H A Dddr.h40 u32 ddrc; member
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra20-pinmux.yaml47 ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls,
/linux/drivers/clk/hisilicon/
H A Dclk-hi3660-stub.c108 DEFINE_CLK_STUB(HI3660_CLK_STUB_DDR, 0x00040309, "clk-ddrc"),
/linux/tools/perf/pmu-events/
H A Dempty-pmu-events.c58 /* offset=3265 */ "hisi_sccl,ddrc\000"
59 /* offset=3280 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000…
148 { 3280 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000\0…
175 .pmu_name = { 3265 /* hisi_sccl,ddrc\000 */ },

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