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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-st.txt57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
109 sd-uhs-ddr50;
H A Dsdhci-am654.yaml103 ti,otap-del-sel-ddr50:
104 description: Output tap delay for SD UHS DDR50 timing
161 ti,itap-del-sel-ddr50:
162 description: Input tap delay for MMC DDR50 timing
H A Dsdhci-omap.txt19 "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104",
H A Dcdns,sdhci.yaml69 cdns,phy-input-delay-sd-uhs-ddr50:
70 description: Value of the delay in the input path for SD UHS DDR50 timing
H A Dmmc-controller.yaml160 sd-uhs-ddr50:
163 SD UHS DDR50 speed is supported.
348 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
H A Dbrcm,sdhci-brcmstb.txt22 sd-uhs-ddr50;
H A Dbrcm,sdhci-brcmstb.yaml92 sd-uhs-ddr50;
H A Dsdhci-am654.txt29 - ti,otap-del-sel-ddr50
H A Dsamsung,exynos-dw-mshc.yaml166 sd-uhs-ddr50;
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih410-b2120.dts41 sd-uhs-ddr50;
H A Dstih418-b2199.dts94 sd-uhs-ddr50;
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra72x-mmc-iodelay.dtsi17 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
90 mmc1_pins_ddr50_rev10: mmc1-ddr50-rev10-pins {
101 mmc1_pins_ddr50_rev20: mmc1-ddr50-rev20-pins {
H A Ddra72-evm.dts94 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
H A Ddra72-evm-revc.dts124 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
H A Ddra76x-mmc-iodelay.dtsi15 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
63 mmc1_pins_ddr50: mmc1-ddr50-pins {
H A Ddra7-evm.dts389 …pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50"…
H A Ddra71-evm.dts203 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
/freebsd/sys/dev/mmc/
H A Dmmc_helpers.c58 if (device_has_property(dev, "sd-uhs-ddr50") && !no_18v) in mmc_parse_sd_speed()
H A Dbridge.h157 #define MMC_CAP_UHS_DDR50 (1 << 10) /* Can do UHS DDR50 */
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-sck-kv-g-revB.dts117 clk-phase-uhs-ddr50 = <126>, <48>;
H A Dzynqmp-sck-kv-g-revB.dtso120 clk-phase-uhs-ddr50 = <126>, <48>;
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-phg.dts243 sd-uhs-ddr50;
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxl-s905x-libretech-cc-v2.dts250 sd-uhs-ddr50;
H A Dmeson-gx-libretech-pc.dtsi381 sd-uhs-ddr50;
H A Dmeson-gxbb-odroidc2.dts350 sd-uhs-ddr50;

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