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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dbrcm,brcmstb-memc-ddr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
16 - brcm,brcmstb-memc-ddr-rev-b.1.x
17 - brcm,brcmstb-memc-ddr-rev-b.2.0
18 - brcm,brcmstb-memc-ddr-rev-b.2.1
19 - brcm,brcmstb-memc-ddr-rev-b.2.2
20 - brcm,brcmstb-memc-ddr-rev-b.2.3
21 - brcm,brcmstb-memc-ddr-rev-b.2.5
22 - brcm,brcmstb-memc-ddr-rev-b.2.6
23 - brcm,brcmstb-memc-ddr-rev-b.2.7
24 - brcm,brcmstb-memc-ddr-rev-b.2.8
[all …]
H A Dcalxeda-ddr-ctrlr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
7 title: Calxeda DDR memory controller
10 The Calxeda DDR memory controller is initialised and programmed by the
20 - calxeda,hb-ddr-ctrl
21 - calxeda,ecx-2000-ddr-ctrl
39 compatible = "calxeda,hb-ddr-ctrl";
H A Dxlnx,versal-ddrmc-edac.yaml7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
24 - description: DDR Memory Controller registers
25 - description: NOC registers corresponding to DDR Memory Controller
H A Drockchip,rk3399-dmc.yaml20 Node to get DDR loading. Refer to
44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
51 For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
318 Defines the power-down idle disable frequency in Hz. When the DDR
324 Defines the self-refresh idle disable frequency in Hz. When the DDR
[all …]
/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mp/sys/
H A Dmetrics.json3 "BriefDescription": "bytes of all masters read from ddr",
11 "BriefDescription": "bytes of all masters write to ddr",
19 "BriefDescription": "bytes of a53 core read from ddr",
27 "BriefDescription": "bytes of a53 core write to ddr",
35 "BriefDescription": "bytes of supermix(m7) core read from ddr",
43 "BriefDescription": "bytes of supermix(m7) write to ddr",
51 "BriefDescription": "bytes of gpu 3d read from ddr",
59 "BriefDescription": "bytes of gpu 3d write to ddr",
67 "BriefDescription": "bytes of gpu 2d read from ddr",
75 "BriefDescription": "bytes of gpu 2d write to ddr",
[all …]
H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
173 "brcm,brcmstb-ddr-phy-v240.2"
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
[all …]
/linux/Documentation/devicetree/bindings/mips/brcm/
H A Dsoc.txt45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
75 memc-ddr@2000 {
79 ddr-phy@6000 {
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
95 - reg : the DDR PHY register range and length
99 ddr-phy@6000 {
[all …]
/linux/drivers/memory/
H A Dbrcmstb_memc.c3 * DDR Self-Refresh Power Down (SRPD) support for Broadcom STB SoCs
176 .compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
180 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.0",
184 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
188 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2",
192 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3",
196 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.5",
200 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.6",
204 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.7",
208 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.8",
[all …]
/linux/arch/mips/include/asm/mach-rc32434/
H A Dddr.h2 * Definitions for the DDR registers
34 /* DDR register structure */
51 /* DDR banks masks */
56 /* DDR bank0 registers */
86 /* DDR bank C registers */
91 /* Custom DDR bank registers */
102 /* DDR QSC registers */
114 /* DDR LLC registers */
126 /* DDR LLFC registers */
132 /* DDR DLLTA registers */
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dqca,ar7100-cpu-intc.yaml13 On most SoC the IRQ controller need to flush the DDR FIFO before running the
15 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
31 qca,ddr-wb-channel-interrupts:
35 qca,ddr-wb-channels:
54 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
55 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
60 #qca,ddr-wb-channel-cells = <1>;
/linux/include/linux/
H A Dfsl-diu-fb.h65 * These are the fields of area descriptor(in DDR memory) for every plane
68 /* Word 0(32-bit) in DDR memory */
81 /* Word 1(32-bit) in DDR memory */
84 /* Word 2(32-bit) in DDR memory */
92 /* Word 3(32-bit) in DDR memory */
100 /* Word 4(32-bit) in DDR memory */
108 /* Word 5(32-bit) in DDR memory */
116 /* Word 6(32-bit) in DDR memory */
122 /* Word 7(32-bit) in DDR memory */
129 /* Word 8(32-bit) in DDR memory */
[all …]
/linux/Documentation/devicetree/bindings/perf/
H A Damlogic,g12-ddr-pmu.yaml4 $id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
7 title: Amlogic G12 DDR performance monitor
13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
21 - amlogic,g12a-ddr-pmu
22 - amlogic,g12b-ddr-pmu
23 - amlogic,sm1-ddr-pmu
49 compatible = "amlogic,g12a-ddr-pmu";
H A Dmarvell-cn10k-ddr.yaml4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
7 title: Marvell CN10K DDR performance monitor
16 - marvell,cn10k-ddr-pmu
34 compatible = "marvell,cn10k-ddr-pmu";
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm7445.dtsi239 memc-ddr@2000 {
240 compatible = "brcm,brcmstb-memc-ddr";
244 ddr-phy@6000 {
245 compatible = "brcm,brcmstb-ddr-phy-v240.1";
250 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
261 memc-ddr@2000 {
262 compatible = "brcm,brcmstb-memc-ddr";
266 ddr-phy@6000 {
267 compatible = "brcm,brcmstb-ddr-phy-v240.1";
272 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h17 /* DDR controller enabled */
30 * Video Frame mapping in DDR
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
145 /* DDR Single Access Page Number */
147 /* DDR-DPR Burst Read Enable */
150 * DDR A/B Select as HOST access
156 * DDR Access Mode Select
157 * 0 Single R/W Access (Host <-> DDR)
287 /* DDR base address of OSD rectangle attribute data */
[all …]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A Dmemory.json11 … code reads and prefetch code read requests that accounts for responses from DDR (local and far)",
14 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",
71 …ble data and L1 prefetch data read requests that accounts for responses from DDR (local and far)",
74 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",
181 …"BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)…
184 "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",
241 … "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)",
244 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",
301 …Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)",
304 "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",
[all …]
/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mn/sys/
H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/
H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/
H A Dddrc.json3 "BriefDescription": "ddr cycles event",
10 "BriefDescription": "ddr read-cycles event",
17 "BriefDescription": "ddr write-cycles event",
24 "BriefDescription": "ddr read event",
31 "BriefDescription": "ddr write event",
/linux/Documentation/devicetree/bindings/clock/
H A Damlogic,meson8-ddr-clkc.yaml4 $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
7 title: Amlogic DDR Clock Controller
15 - amlogic,meson8-ddr-clkc
16 - amlogic,meson8b-ddr-clkc
43 compatible = "amlogic,meson8-ddr-clkc";
H A Dmvebu-core-clock.txt12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst219 DDR (Double Data Rate) and DLVR (Digital Linear Voltage Regulator)
240 DRAM devices of DDR IO interface and their power plane can generate EMI
242 mechanism by which DDR data rates can be changed if several conditions
243 are met: there is strong RFI interference because of DDR; CPU power
244 management has no other restriction in changing DDR data rates;
245 PC ODMs enable this feature (real time DDR RFI Mitigation referred to as
246 DDR-RFIM) for Wi-Fi from BIOS.
280 Request the restriction of specific DDR data rate and set this
288 Restricted DDR data rate for RFI protection: Lower Limit
291 Restricted DDR data rate for RFI protection: Upper Limit
[all …]
/linux/drivers/irqchip/
H A Dirq-ath79-cpu.c27 * This array map the interrupt lines to the DDR write buffer channels.
63 node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells"); in ar79_cpu_intc_of_init()
70 node, "qca,ddr-wb-channel-interrupts", i, &irq); in ar79_cpu_intc_of_init()
75 node, "qca,ddr-wb-channels", in ar79_cpu_intc_of_init()
76 "#qca,ddr-wb-channel-cells", in ar79_cpu_intc_of_init()
/linux/arch/mips/boot/dts/qca/
H A Dar9132.dtsi28 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
52 compatible = "qca,ar9132-ddr-controller",
53 "qca,ar7240-ddr-controller";
56 #qca,ddr-wb-channel-cells = <1>;
98 clock-output-names = "cpu", "ddr", "ahb";

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