| /freebsd/sys/geom/part/ |
| H A D | g_part_apm.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2006-2008 Marcel Moolenaar
49 FEATURE(geom_part_apm, "GEOM partitioning class for Apple-style partitions");
53 struct apm_ddr ddr; member
124 apm_parse_type(const char *type, char *buf, size_t bufsz) in apm_parse_type() argument
128 if (type[0] == '!') { in apm_parse_type()
129 type++; in apm_parse_type()
130 if (strlen(type) > bufsz) in apm_parse_type()
132 if (!strcmp(type, APM_ENT_TYPE_SELF) || in apm_parse_type()
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/devfreq/ |
| H A D | rk3399_dmc.txt | 4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
15 - rockchip,pmu: Phandle to the syscon managing the "PMU general register
19 - interrupts: The CPU interrupt number. The interrupt specifier
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
[all...] |
| H A D | ath79-ddr-controller.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the AR7xxx and AR9xxx families provides an interface
4 to flush the FIFO between various devices and the DDR. This is mainly used
10 - compatible: has to be "qca,<soc-type>-ddr-controller",
11 "qca,[ar7100|ar7240]-ddr-controller" as fallback.
12 On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
13 fallback, otherwise "qca,ar7240-ddr-controller" should be used.
14 - reg: Base address and size of the controller's memory area
15 - #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
20 ddr_ctrl: memory-controller@18000000 {
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|
| H A D | samsung,s5pv210-dmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/samsung,s5pv210-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Dynamic Memory Controller interfaces external JEDEC DDR-type SDRAM.
17 const: samsung,s5pv210-dmc
23 - compatible
24 - reg
29 - |
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| /freebsd/sys/dev/clk/allwinner/ |
| H A D | ccu_a13.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/reset/sun5i-ccu.h>
50 /* Non-exported clocks */
101 CCU_GATE(CLK_DRAM_AXI, "axi-dram", "axi", 0x5c, 0)
103 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
104 CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1)
105 CCU_GATE(CLK_AHB_OHCI, "ahb-ohci", "ahb", 0x60, 2)
106 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | rohm,bd9576-pmic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd9576-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 powering the R-Car series processors.
21 - rohm,bd9576
22 - rohm,bd9573
32 rohm,vout1-en-low:
35 controlled by a GPIO. This is dictated by state of vout1-en pin during
[all …]
|
| H A D | rohm,bd9571mwv.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marek.vasut@gmail.com>
15 - rohm,bd9571mwv
16 - rohm,bd9574mwf
24 interrupt-controller: true
26 '#interrupt-cells':
29 gpio-controller: true
31 '#gpio-cells':
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr-channel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
24 - jedec,lpddr5-channel
26 io-width:
[all …]
|
| H A D | lpddr2-timings.txt | 1 * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
4 - compatible : Should be "jedec,lpddr2-timings"
5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
11 data-sheet of the device for a given speed-bin. All these properties are
12 of type <u32> and the default unit is ps (pico seconds). Parameters with
13 a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
14 - tRCD
15 - tWR
16 - tRAS-min
[all …]
|
| H A D | lpddr3-timings.txt | 1 * AC timing parameters of LPDDR3 memories for a given speed-bin.
6 - compatible : Should be "jedec,lpddr3-timings"
7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
13 data-sheet of the device for a given speed-bin. All these properties are
14 of type <u32> and the default unit is ps (pico seconds).
15 - tRFC
16 - tRRD
17 - tRPab
18 - tRPpb
[all …]
|
| H A D | lpddr3.txt | 1 * LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
4 - compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
5 Example "<vendor>,<type>" values:
8 - density : <u32> representing density in Mb (Mega bits)
9 - io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
10 - #address-cells: Must be set to 1
11 - #size-cells: Must be set to 0
15 - manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5
16 - revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7
19 timing parameters of the DDR device in terms of number of clock cycles.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | mmc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cell
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | dcsr.txt | 21 - compatible
23 Value type: <string>
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
29 Value type: <u32>
33 - #size-cells
35 Value type
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| /freebsd/sys/contrib/device-tree/Bindings/ddr/ |
| H A D | lpddr2-timings.txt | 1 * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
4 - compatible : Should be "jedec,lpddr2-timings"
5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
11 data-sheet of the device for a given speed-bin. All these properties are
12 of type <u32> and the default unit is ps (pico seconds). Parameters with
13 a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
14 - tRCD
15 - tWR
16 - tRAS-min
[all …]
|
| H A D | lpddr3-timings.txt | 1 * AC timing parameters of LPDDR3 memories for a given speed-bin.
6 - compatible : Should be "jedec,lpddr3-timings"
7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
13 data-sheet of the device for a given speed-bin. All these properties are
14 of type <u32> and the default unit is ps (pico seconds).
15 - tRFC
16 - tRRD
17 - tRPab
18 - tRPpb
[all …]
|
| H A D | lpddr2.txt | 1 * LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
4 - compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
5 "jedec,lpddr2-s4"
7 "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
9 "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
11 "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
13 - density : <u32> representing density in Mb (Mega bits)
15 - io-width : <u32> representing bus width. Possible values are 8, 16, and 32
20 timing parameters of the DDR device in terms of number of clock cycles.
21 These values shall be obtained from the device data-sheet.
[all …]
|
| H A D | lpddr3.txt | 1 * LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
4 - compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
5 Example "<vendor>,<type>" values:
8 - density : <u32> representing density in Mb (Mega bits)
9 - io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
10 - #address-cells: Must be set to 1
11 - #size-cells: Must be set to 0
15 - manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5
16 - revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7
19 timing parameters of the DDR device in terms of number of clock cycles.
[all …]
|
| /freebsd/usr.bin/mkimg/ |
| H A D | apm.c | 1 /*-
63 struct apm_ddr *ddr; in apm_write() local
71 ddr = (void *)buf; in apm_write()
72 be16enc(&ddr->ddr_sig, APM_DDR_SIG); in apm_write()
73 be16enc(&ddr->ddr_blksize, secsz); in apm_write()
74 be32enc(&ddr->ddr_blkcount, imgsz); in apm_write()
78 be16enc(&ent->ent_sig, APM_ENT_SIG); in apm_write()
79 be32enc(&ent->ent_pmblkcnt, nparts + 1); in apm_write()
80 be32enc(&ent->ent_start, 1); in apm_write()
81 be32enc(&ent->ent_size, nparts + 1); in apm_write()
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/fsl/ |
| H A D | imx8m-ddrc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX8M DDR Controller
10 - Peng Fan <peng.fan@nxp.com>
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
18 switching is implemented by TF-A code which runs from a SRAM area.
27 - enum:
28 - fsl,imx8mn-ddrc
[all …]
|
| H A D | fsl,ddr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale DDR memory controller
10 - Borislav Petkov <bp@alien8.de>
11 - York Sun <york.sun@nxp.com>
15 pattern: "^memory-controller@[0-9a-f]+$"
19 - items:
20 - enum:
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | pfuze100.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_nb_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
485 /* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity
512 By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other…
513 …t by primary CPU as part of the initialization process will initiate power-on-reset to this specif…
[all …]
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| /freebsd/sys/dev/sfxge/common/ |
| H A D | efx_regs_mcdi_aoe.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2008-2018 Solarflare Communications Inc. All rights reserved.
152 /* enum: PHY read connection from FC - may be not required */
154 /* enum: PHY read flags from FC - may be not required */
172 /* enum: MAC Set command - same as MC_CMD_SET_MAC */
186 /* enum: Internal Siena-facing FPGA ports. */
357 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */
368 /* The type of the SFP+ Module. For later cards with QSFP modules, this field
369 * is unused and the type is communicated by other means.
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | fsl-ls208xa.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
[all …]
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