| /linux/drivers/clk/hisilicon/ |
| H A D | clkdivider-hi6220.c | 49 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_recalc_rate() local
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
55 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in hi6220_clkdiv_recalc_rate()
61 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_determine_rate() local
63 return divider_determine_rate(hw, req, dclk->table, dclk->width, in hi6220_clkdiv_determine_rate()
73 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_set_rate() local
75 value = divider_get_val(rate, parent_rate, dclk->table, in hi6220_clkdiv_set_rate()
76 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in hi6220_clkdiv_set_rate()
[all …]
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| /linux/Documentation/devicetree/bindings/display/ |
| H A D | solomon,ssd1307fb.yaml | 87 solomon,dclk-div:
94 solomon,dclk-frq:
138 solomon,dclk-div:
140 solomon,dclk-frq:
156 solomon,dclk-div:
158 solomon,dclk-frq:
174 solomon,dclk-div:
176 solomon,dclk-frq:
192 solomon,dclk-div:
194 solomon,dclk-frq:
[all …]
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| /linux/sound/soc/meson/ |
| H A D | axg-pdm.c | 94 struct clk *dclk; member
186 /* Max sample counter value per half period of dclk */ in axg_pdm_set_sample_pointer()
188 clk_get_rate(priv->dclk) * 2); in axg_pdm_set_sample_pointer()
253 ret = clk_set_rate(priv->dclk, rate * os); in axg_pdm_hw_params()
255 dev_err(dai->dev, "failed to set dclk\n"); in axg_pdm_hw_params()
276 ret = clk_prepare_enable(priv->dclk); in axg_pdm_startup()
278 dev_err(dai->dev, "enabling dclk failed\n"); in axg_pdm_startup()
294 clk_disable_unprepare(priv->dclk); in axg_pdm_shutdown()
618 priv->dclk = devm_clk_get(dev, "dclk"); in axg_pdm_probe()
619 if (IS_ERR(priv->dclk)) in axg_pdm_probe()
[all …]
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_bw.c | 53 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; member
87 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); in dg1_mchbar_read_qgv_point_info()
91 sp->dclk *= 2; in dg1_mchbar_read_qgv_point_info()
93 if (sp->dclk == 0) in dg1_mchbar_read_qgv_point_info()
114 u16 dclk; in icl_pcode_read_qgv_point_info() local
123 dclk = val & 0xffff; in icl_pcode_read_qgv_point_info()
124 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(display) >= 12 ? 500 : 0), in icl_pcode_read_qgv_point_info()
216 u16 dclk; in mtl_read_qgv_point_info() local
220 dclk in mtl_read_qgv_point_info()
371 u16 dclk = 0; icl_sagv_max_dclk() local
[all...] |
| /linux/drivers/gpu/drm/radeon/ |
| H A D | rs780_dpm.c | 571 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
588 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rs780_parse_pplib_non_clock_info()
731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
737 rps->dclk = RS780_DEFAULT_DCLK_FREQ; in rs780_parse_pplib_non_clock_info()
944 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
993 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
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| H A D | sumo_dpm.c | 822 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
839 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_before_set_eng_clock()
857 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_after_set_eng_clock()
1413 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in sumo_parse_pplib_non_clock_info()
1416 rps->dclk = 0; in sumo_parse_pplib_non_clock_info()
1803 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1826 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1834 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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| H A D | trinity_dpm.c | 850 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
863 (rps1->dclk == rps2->dclk) && in trinity_uvd_clocks_equal()
895 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
906 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1411 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) in trinity_get_uvd_clock_index()
1645 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in trinity_parse_pplib_non_clock_info()
1648 rps->dclk = 0; in trinity_parse_pplib_non_clock_info()
1889 pi->sys_info.uvd_clock_table_entries[i].dclk = in trinity_parse_sys_info_table()
1972 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1997 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
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| H A D | rv6xx_dpm.c | 1519 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1536 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1804 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1807 rps->dclk = 0; in rv6xx_parse_pplib_non_clock_info()
2014 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2046 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
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| H A D | rv770_dpm.c | 1441 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_before_set_eng_clock()
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1458 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_after_set_eng_clock()
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2156 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rv7xx_parse_pplib_non_clock_info()
2159 rps->dclk = 0; in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2165 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2441 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2485 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
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| /linux/drivers/video/fbdev/riva/ |
| H A D | nv_driver.c | 276 unsigned long dclk = 0; in riva_get_maxdclk() local
286 dclk = 800000; in riva_get_maxdclk()
288 dclk = 1000000; in riva_get_maxdclk()
294 dclk = 1000000; in riva_get_maxdclk()
303 dclk = 800000; in riva_get_maxdclk()
306 dclk = 1000000; in riva_get_maxdclk()
311 return dclk; in riva_get_maxdclk()
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| /linux/drivers/gpu/drm/renesas/rz-du/ |
| H A D | rzg2l_du_crtc.c | 71 clk_prepare_enable(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_set_display_timing()
72 clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock); in rzg2l_du_crtc_set_display_timing()
209 clk_disable_unprepare(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_put()
401 rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk"); in rzg2l_du_crtc_create()
402 if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) { in rzg2l_du_crtc_create()
404 return PTR_ERR(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_create()
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| /linux/drivers/video/fbdev/core/ |
| H A D | fbmon.c | 551 DPRINTK(" mode exceed max DCLK\n"); in get_std_timing()
775 DPRINTK(" H: %d-%dKHz V: %d-%dHz DCLK: %dMHz\n", in fb_get_monitor_limits()
1022 u32 dclk; member
1092 * @dclk: pixelclock in Hz
1104 * where: h_period = SQRT(100 - C + (0.4 * xres * M)/dclk) + C - 100
1110 static u32 fb_get_hblank_by_dclk(u32 dclk, u32 xres) in fb_get_hblank_by_dclk() argument
1114 dclk /= 1000; in fb_get_hblank_by_dclk()
1117 h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk); in fb_get_hblank_by_dclk()
1161 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1172 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_hfreq()
[all …]
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | amlogic,axg-pdm.yaml | 37 - const: dclk
81 clock-names = "pclk", "dclk", "sysclk";
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| /linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_drm_vop.c | 177 /* vop dclk */
178 struct clk *dclk; member
182 /* vop dclk reset */
635 ret = clk_enable(vop->dclk); in vop_enable()
703 clk_disable(vop->dclk); in vop_enable()
775 clk_disable(vop->dclk); in vop_crtc_atomic_disable()
1243 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); in vop_crtc_mode_fixup()
1245 rate = clk_round_rate(vop->dclk, in vop_crtc_mode_fixup()
1477 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); in vop_crtc_atomic_enable()
2016 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); in vop_initial()
[all …]
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| H A D | rockchip_drm_vop2.c | 961 clk_set_parent(vp->dclk, vp->dclk_src); in vop2_crtc_atomic_disable()
963 clk_disable_unprepare(vp->dclk); in vop2_crtc_atomic_disable()
1658 ret = clk_prepare_enable(vp->dclk); in vop2_crtc_atomic_enable()
1660 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n", in vop2_crtc_atomic_enable()
1688 * process multi(1/2/4/8) pixels per cycle, so the dclk feed by the in vop2_crtc_atomic_enable()
1757 * Switch to HDMI PHY PLL as DCLK source for display modes up in vop2_crtc_atomic_enable()
1772 vp->dclk_src = clk_get_parent(vp->dclk); in vop2_crtc_atomic_enable()
1774 ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0); in vop2_crtc_atomic_enable()
1787 vp->dclk_src = clk_get_parent(vp->dclk); in vop2_crtc_atomic_enable()
1789 ret = clk_set_parent(vp->dclk, vop in vop2_crtc_atomic_enable()
[all...] |
| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu_v13_0_5_ppsmc.h | 52 #define PPSMC_MSG_SetSoftMaxVcn 17 ///< Set soft max for VCN clocks (VCLK and DCLK)
59 #define PPSMC_MSG_SetSoftMinVcn 24 ///< Set soft min for VCN clocks (VCLK and DCLK)
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| H A D | smu_v13_0_1_ppsmc.h | 65 …efine PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)
75 …efine PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK)
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| H A D | smu_v13_0_4_ppsmc.h | 74 …efine PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)
87 …efine PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK)
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | power_state.h | 145 uint32_t DCLK; member
185 unsigned long dclk; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.h | 39 uint32_t dclk; member
120 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
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| /linux/drivers/clk/mvebu/ |
| H A D | armada-39x.c | 21 * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
88 { .id = A390_CPU_TO_DCLK, .name = "dclk" },
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| /linux/drivers/video/fbdev/ |
| H A D | ssd1307fb.c | 339 u32 precharge, dclk, com_invdir, compins; in ssd1307fb_init() local
404 dclk = ((par->dclk_div - 1) & 0xf) | (par->dclk_frq & 0xf) << 4; in ssd1307fb_init()
405 ret = ssd1307fb_write_cmd(par->client, dclk); in ssd1307fb_init()
663 if (device_property_read_u32(dev, "solomon,dclk-div", &par->dclk_div)) in ssd1307fb_probe()
665 if (device_property_read_u32(dev, "solomon,dclk-frq", &par->dclk_frq)) in ssd1307fb_probe()
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| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | uncore-power.json | 8 "PublicDescription": "PCU Clockticks: The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
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| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | uncore-power.json | 8 …ed while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a consta…
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| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | uncore-power.json | 8 "PublicDescription": "PCU Clockticks: The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
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