| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-timecard | 25 DCF adjustments from external DCF signal
43 DCF signal is sent to the DCF module
63 DCF output is from the PHC, in DCF format
288 Description: (RW) The DCF and IRIG output signals are in UTC, while the
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| /linux/drivers/block/drbd/ |
| H A D | drbd_debugfs.c | 796 #define DCF(name) do { \ in drbd_debugfs_device_attr() macro
803 DCF(oldest_requests); in drbd_debugfs_device_attr()
804 DCF(act_log_extents); in drbd_debugfs_device_attr()
805 DCF(resync_extents); in drbd_debugfs_device_attr()
806 DCF(data_gen_id); in drbd_debugfs_device_attr()
807 DCF(ed_gen_id); in drbd_debugfs_device_attr()
808 #undef DCF in drbd_debugfs_device_attr()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_pp_smu.h | 122 * when DF is in cstate, dcf clock is further divided down
182 * when DF is in cstate, dcf clock is further divided down
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| H A D | dm_services_types.h | 86 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
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| /linux/drivers/net/wireless/ti/wl1251/ |
| H A D | init.h | 46 * slot number setting to start transmission at DIFS interval - normal DCF
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.c | 71 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
72 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep…
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.c | 86 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
87 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep…
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| /linux/drivers/net/wireless/ath/ath5k/ |
| H A D | qcu.c | 20 Queue Control Unit, DCF Control Unit Functions
31 * DOC: Queue Control Unit (QCU)/DCF Control Unit (DCU) functions
320 * Set DCF properties for the given transmit queue on DCU
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
45 finishes, a DCF interrupt is triggered.
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 244 //DCF Clock in rv1_update_clocks()
256 /* make sure dcf clk is before dpp clk to in rv1_update_clocks()
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| /linux/Documentation/fb/ |
| H A D | framebuffer.rst | 262 < name > DCF HR SH1 SH2 HFL VR SV1 SV2 VFL
280 pixclock = 1000000 / DCF
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| /linux/drivers/net/wireless/intersil/p54/ |
| H A D | p54.h | 188 /* (e)DCF / QOS state */
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| H A D | lmac.h | 544 /* e/v DCF setup */
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 302 /* only pipe 0 is read for voltage and dcf/soc clocks */ in calculate_wm_set_for_vlevel()
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| /linux/drivers/platform/x86/ |
| H A D | lg-laptop.c | 62 #define WMI_METHOD_WMBB "2B4F501A-BD3C-4394-8DCF-00A7D2BC8210"
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| /linux/drivers/net/wireless/ti/wlcore/ |
| H A D | conf.h | 294 * DCF access */
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 223 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL); //dcf deep sleep divider in vg_dump_clk_registers_internal()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 291 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider in rn_dump_clk_registers_internal()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1795 /* only pipe 0 is read for voltage and dcf/soc clocks */ in dcn20_calculate_wm()
1871 // Accounting for SOC/DCF relationship, we can go as high as in dcn20_update_bounding_box()
2217 /* only pipe 0 is read for voltage and dcf/soc clocks */ in calculate_wm_set_for_vlevel()
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| /linux/tools/testing/selftests/tc-testing/tc-tests/actions/ |
| H A D | mpls.json | 1232 "id": "3dcf",
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu10_hwmgr.c | 199 "Attempt to set DCF Clock Failed!", return -EINVAL); in smu10_set_clock_limit()
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| /linux/drivers/usb/serial/ |
| H A D | ftdi_sio_ids.h | 308 #define FTDI_ELV_UDF77_PID 0xFB5E /* USB DCF Funkuhr (UDF 77) */
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| /linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| H A D | d11.h | 1371 * Receive Frame Data Header for 802.11b DCF-only frames
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 74 /* default DCF CLK DPM on RV*/
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 2364 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock in init_soc_bounding_box()
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