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/linux/arch/m68k/ifpsp060/
H A Dpfpsp.sa1 dc.l $60ff0000,$17400000,$60ff0000,$15f40000
2 dc.l $60ff0000,$02b60000,$60ff0000,$04700000
3 dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000
4 dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000
5 dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f
10 dc.l $00044e74,$00042f00,$203afef2,$487b0930
[all …]
H A Dfplsp.sa1 dc.l $60ff0000,$238e0000,$60ff0000,$24200000
2 dc.l $60ff0000,$24b60000,$60ff0000,$11060000
3 dc.l $60ff0000,$11980000,$60ff0000,$122e0000
4 dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000
5 dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000
6 dc.l $60ff0000,$13400000,$60ff0000,$13d60000
7 dc.l $60ff0000,$05ae0000,$60ff0000,$06400000
8 dc.l $60ff0000,$06d60000,$60ff0000,$213e0000
9 dc.l $60ff0000,$21d00000,$60ff0000,$22660000
10 dc.l $60ff0000,$16160000,$60ff0000,$16a80000
[all …]
H A Ditest.sa1 dc.l $60ff0000,$005c5465,$7374696e,$67203638
2 dc.l $30363020,$49535020,$73746172,$7465643a
3 dc.l $0a007061,$73736564,$0a002066,$61696c65
4 dc.l $640a0000,$4a80660e,$487affe8,$61ff0000
5 dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f
6 dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56
7 dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c
8 dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff
9 dc.l $00004f58,$588f61ff,$000000f0,$61ffffff
10 dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff
[all …]
H A Dftest.sa1 dc.l $60ff0000,$00d40000,$60ff0000,$016c0000
2 dc.l $60ff0000,$01a80000,$54657374,$696e6720
3 dc.l $36383036,$30204650,$53502073,$74617274
4 dc.l $65643a0a,$00546573,$74696e67,$20363830
5 dc.l $36302046,$50535020,$756e696d,$706c656d
6 dc.l $656e7465,$6420696e,$73747275,$6374696f
7 dc.l $6e207374,$61727465,$643a0a00,$54657374
8 dc.l $696e6720,$36383036,$30204650,$53502065
9 dc.l $78636570,$74696f6e,$20656e61,$626c6564
10 dc.l $20737461,$72746564,$3a0a0070,$61737365
[all …]
H A Dilsp.sa1 dc.l $60ff0000,$01fe0000,$60ff0000,$02080000
2 dc.l $60ff0000,$04900000,$60ff0000,$04080000
3 dc.l $60ff0000,$051e0000,$60ff0000,$053c0000
4 dc.l $60ff0000,$055a0000,$60ff0000,$05740000
5 dc.l $60ff0000,$05940000,$60ff0000,$05b40000
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
10 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
[all …]
/linux/drivers/dma/
H A Dtxx9dmac.c24 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc) in __dma_regs() argument
26 return dc->ch_regs; in __dma_regs()
30 const struct txx9dmac_chan *dc) in __dma_regs32() argument
32 return dc->ch_regs; in __dma_regs32()
35 #define channel64_readq(dc, name) \ argument
36 __raw_readq(&(__dma_regs(dc)->name))
37 #define channel64_writeq(dc, name, val) \ argument
38 __raw_writeq((val), &(__dma_regs(dc)->name))
39 #define channel64_readl(dc, name) \ argument
40 __raw_readl(&(__dma_regs(dc)->name))
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h31 void dcn20_log_color_state(struct dc *dc,
38 struct dc *dc,
41 struct dc *dc,
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
45 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
49 void dcn20_program_output_csc(struct dc *dc,
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
59 struct dc *dc,
[all …]
H A Ddcn20_hwseq.c75 void dcn20_log_color_state(struct dc *dc, in dcn20_log_color_state() argument
78 struct dc_context *dc_ctx = dc->ctx; in dcn20_log_color_state()
79 struct resource_pool *pool = dc->res_pool; in dcn20_log_color_state()
151 dc->caps.color.dpp.input_lut_shared, in dcn20_log_color_state()
152 dc->caps.color.dpp.icsc, in dcn20_log_color_state()
153 dc->caps.color.dpp.dgam_ram, in dcn20_log_color_state()
154 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn20_log_color_state()
155 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn20_log_color_state()
156 dc->caps.color.dpp.dgam_rom_caps.gamma2_2, in dcn20_log_color_state()
157 dc->caps.color.dpp.dgam_rom_caps.pq, in dcn20_log_color_state()
[all …]
/linux/drivers/tty/
H A Dnozomi.c315 struct nozomi *dc; member
463 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
465 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
472 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
473 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
474 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
475 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
476 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
477 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
478 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
[all …]
/linux/drivers/md/
H A Ddm-delay.c59 struct delay_c *dc = timer_container_of(dc, t, delay_timer); in handle_delayed_timer() local
61 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
64 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
66 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
69 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
71 return !!dc->worker; in delay_is_fast()
86 static void flush_delayed_bios(struct delay_c *dc, bool flush_all) in flush_delayed_bios() argument
95 mutex_lock(&dc->process_bios_lock); in flush_delayed_bios()
96 spin_lock(&dc->delayed_bios_lock); in flush_delayed_bios()
97 list_replace_init(&dc->delayed_bios, &local_list); in flush_delayed_bios()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c29 #include "dc.h"
93 dc->ctx
96 dc->ctx->logger
103 * DC is the OS-agnostic component of the amdgpu DC driver.
105 * DC maintains and validates a set of structs representing the state of the
108 * Main DC HW structs:
110 * struct dc - The central struct. One per driver. Created on driver load,
114 * Used as a backpointer by most other structs in dc.
127 * Main dc state structs:
130 * these structs in dc->current_state representing the currently programmed state.
[all …]
H A Ddc_stream.c28 #include "dc.h"
37 #define DC_LOGGER dc->ctx->logger
56 if (stream->ctx->dc->caps.dual_link_dvi && in update_stream_signal()
221 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign && in dc_copy_stream()
222 !new_stream->ctx->dc->config.unify_link_enc_assignment) in dc_copy_stream()
234 * The given stream is expected to exist in dc->current_state. Otherwise, NULL
240 struct dc *dc = stream->ctx->dc; in dc_stream_get_status() local
241 return dc_state_get_stream_status(dc->current_state, stream); in dc_stream_get_status()
247 struct dc *dc = stream->ctx->dc; in dc_stream_get_status_const() local
249 return dc_state_get_stream_status(dc->current_state, stream); in dc_stream_get_status_const()
[all …]
H A Ddc_state.c43 dc->ctx->logger
184 static void init_state(struct dc *dc, struct dc_state *state) in init_state() argument
187 * initialize and obtain IP and SOC the base DML instance from DC is in init_state()
190 memcpy(&state->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); in init_state()
194 struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params) in dc_state_create() argument
203 init_state(dc, state); in dc_state_create()
204 dc_state_construct(dc, state); in dc_state_create()
208 if (dc->debug.using_dml2) { in dc_state_create()
209 if (!dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2)) { in dc_state_create()
214 …if (dc->caps.dcmode_power_limits_present && !dml2_create(dc, &dc->dml2_dc_power_options, &state->b… in dc_state_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h57 struct dc *dc; member
63 struct dc *dc; member
74 const struct dc *dc; member
80 struct dc *dc; member
85 struct dc *dc; member
113 struct dc *dc; member
119 struct dc *dc; member
151 const struct dc *dc; member
156 struct dc *dc; member
178 struct dc *dc; member
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c65 dc->ctx->logger
72 static void enable_memory_low_power(struct dc *dc) in enable_memory_low_power() argument
74 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power()
77 if (dc->debug.enable_mem_low_power.bits.dmcu) { in enable_memory_low_power()
79 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { in enable_memory_low_power()
85 if (dc->debug.enable_mem_low_power.bits.optc) { in enable_memory_low_power()
90 if (dc->debug.enable_mem_low_power.bits.vga) { in enable_memory_low_power()
95 if (dc->debug.enable_mem_low_power.bits.mpc && in enable_memory_low_power()
96 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) in enable_memory_low_power()
97 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c78 static void enable_memory_low_power(struct dc *dc)
80 struct dce_hwseq *hws = dc->hwseq;
83 if (dc->debug.enable_mem_low_power.bits.dmcu) {
85 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
91 if (dc->debug.enable_mem_low_power.bits.optc) {
96 if (dc->debug.enable_mem_low_power.bits.vga) {
101 if (dc->debug.enable_mem_low_power.bits.mpc &&
102 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)
103 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
105 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd…
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.h31 struct dc;
44 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
46 void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
53 bool dcn32_set_input_transfer_func(struct dc *dc,
60 bool dcn32_set_output_transfer_func(struct dc *dc,
64 void dcn32_init_hw(struct dc *dc);
66 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
68 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
70 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);
[all …]
H A Ddcn32_hwseq.c64 dc->ctx->logger
78 struct dc *dc = hws->ctx->dc; in dcn32_dsc_pg_control() local
80 if (dc->debug.disable_dsc_power_gate) in dcn32_dsc_pg_control()
83 if (!dc->debug.enable_double_buffered_dsc_pg_support) in dcn32_dsc_pg_control()
86 if (dc->debug.ignore_pg) in dcn32_dsc_pg_control()
172 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn32_hubp_pg_control()
175 if (hws->ctx->dc->debug.ignore_pg) in dcn32_hubp_pg_control()
204 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) in dcn32_check_no_memory_request_for_cab() argument
209 for (i = 0; i < dc->current_state->stream_count; i++) { in dcn32_check_no_memory_request_for_cab()
210 if ((dc->current_state->stream_status[i].plane_count) && in dcn32_check_no_memory_request_for_cab()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A DMakefile47 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
48 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
49 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
50 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
51 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
52 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
53 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
54 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
55 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) $(frame_warn_flag)
56 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c68 dc->ctx->logger
75 void dcn30_log_color_state(struct dc *dc, in dcn30_log_color_state() argument
78 struct dc_context *dc_ctx = dc->ctx; in dcn30_log_color_state()
79 struct resource_pool *pool = dc->res_pool; in dcn30_log_color_state()
160 dc->caps.color.dpp.input_lut_shared, in dcn30_log_color_state()
161 dc->caps.color.dpp.icsc, in dcn30_log_color_state()
162 dc->caps.color.dpp.dgam_ram, in dcn30_log_color_state()
163 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn30_log_color_state()
164 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn30_log_color_state()
165 dc->caps.color.dpp.dgam_rom_caps.gamma2_2, in dcn30_log_color_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c28 #include "dc.h"
40 dc->ctx->logger
318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
453 const struct dc *dc, in dcn_bw_calc_rq_dlg_ttu() argument
458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu()
497 input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu()
500 // dc->dml.logger = pool->base.logger; in dcn_bw_calc_rq_dlg_ttu()
638 static bool dcn_bw_apply_registry_override(struct dc *dc) in dcn_bw_apply_registry_override() argument
642 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns in dcn_bw_apply_registry_override()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c51 dc->ctx->logger
58 void dcn401_initialize_min_clocks(struct dc *dc) in dcn401_initialize_min_clocks() argument
60 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
63 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
64 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
65 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
66 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn401_initialize_min_clocks()
67 if (dc->debug.disable_boot_optimizations) { in dcn401_initialize_min_clocks()
68 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn401_initialize_min_clocks()
75 if (dc->clk_mgr->funcs->get_dispclk_from_dentist) { in dcn401_initialize_min_clocks()
[all …]
/linux/drivers/gpu/drm/tegra/
H A Ddc.c33 #include "dc.h"
51 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
55 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
56 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
57 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
80 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
88 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
94 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
97 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
99 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c89 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
102 void dcn10_wait_for_pipe_update_if_needed(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface… in dcn10_wait_for_pipe_update_if_needed() argument
128 dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start, in dcn10_wait_for_pipe_update_if_needed()
131 dc->hwss.get_position(&pipe_ctx, 1, &position); in dcn10_wait_for_pipe_update_if_needed()
178 void dcn10_set_wait_for_update_needed_for_pipe(struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn10_set_wait_for_update_needed_for_pipe() argument
189 dc->hwss.get_position(&pipe_ctx, 1, &position); in dcn10_set_wait_for_update_needed_for_pipe()
192 dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start, in dcn10_set_wait_for_update_needed_for_pipe()
220 void dcn10_lock_all_pipes(struct dc *dc, in dcn10_lock_all_pipes() argument
229 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
230 old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
[all …]
/linux/drivers/scsi/esas2r/
H A Desas2r_disc.c291 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_queue_event() local
298 dc->disc_evt |= disc_evt; in esas2r_disc_queue_event()
314 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_start_port() local
326 if (dc->disc_evt) { in esas2r_disc_start_port()
352 esas2r_trace("disc_evt: %d", dc->disc_evt); in esas2r_disc_start_port()
354 dc->flags = 0; in esas2r_disc_start_port()
357 dc->flags |= DCF_POLLED; in esas2r_disc_start_port()
359 rq->interrupt_cx = dc; in esas2r_disc_start_port()
363 if (dc->disc_evt & DCDE_DEV_SCAN) { in esas2r_disc_start_port()
364 dc->disc_evt &= ~DCDE_DEV_SCAN; in esas2r_disc_start_port()
[all …]

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