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/linux/arch/m68k/ifpsp060/
H A Dpfpsp.sa1 dc.l $60ff0000,$17400000,$60ff0000,$15f40000
2 dc.l $60ff0000,$02b60000,$60ff0000,$04700000
3 dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000
4 dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000
5 dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f
10 dc.l $00044e74,$00042f00,$203afef2,$487b0930
[all …]
H A Dfplsp.sa1 dc.l $60ff0000,$238e0000,$60ff0000,$24200000
2 dc.l $60ff0000,$24b60000,$60ff0000,$11060000
3 dc.l $60ff0000,$11980000,$60ff0000,$122e0000
4 dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000
5 dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000
6 dc.l $60ff0000,$13400000,$60ff0000,$13d60000
7 dc.l $60ff0000,$05ae0000,$60ff0000,$06400000
8 dc.l $60ff0000,$06d60000,$60ff0000,$213e0000
9 dc.l $60ff0000,$21d00000,$60ff0000,$22660000
10 dc.l $60ff0000,$16160000,$60ff0000,$16a80000
[all …]
H A Ditest.sa1 dc.l $60ff0000,$005c5465,$7374696e,$67203638
2 dc.l $30363020,$49535020,$73746172,$7465643a
3 dc.l $0a007061,$73736564,$0a002066,$61696c65
4 dc.l $640a0000,$4a80660e,$487affe8,$61ff0000
5 dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f
6 dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56
7 dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c
8 dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff
9 dc.l $00004f58,$588f61ff,$000000f0,$61ffffff
10 dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff
[all …]
H A Dftest.sa1 dc.l $60ff0000,$00d40000,$60ff0000,$016c0000
2 dc.l $60ff0000,$01a80000,$54657374,$696e6720
3 dc.l $36383036,$30204650,$53502073,$74617274
4 dc.l $65643a0a,$00546573,$74696e67,$20363830
5 dc.l $36302046,$50535020,$756e696d,$706c656d
6 dc.l $656e7465,$6420696e,$73747275,$6374696f
7 dc.l $6e207374,$61727465,$643a0a00,$54657374
8 dc.l $696e6720,$36383036,$30204650,$53502065
9 dc.l $78636570,$74696f6e,$20656e61,$626c6564
10 dc.l $20737461,$72746564,$3a0a0070,$61737365
[all …]
H A Dilsp.sa1 dc.l $60ff0000,$01fe0000,$60ff0000,$02080000
2 dc.l $60ff0000,$04900000,$60ff0000,$04080000
3 dc.l $60ff0000,$051e0000,$60ff0000,$053c0000
4 dc.l $60ff0000,$055a0000,$60ff0000,$05740000
5 dc.l $60ff0000,$05940000,$60ff0000,$05b40000
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
10 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
[all …]
/linux/drivers/dma/
H A Dtxx9dmac.c24 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc) in __dma_regs() argument
26 return dc->ch_regs; in __dma_regs()
30 const struct txx9dmac_chan *dc) in __dma_regs32() argument
32 return dc->ch_regs; in __dma_regs32()
35 #define channel64_readq(dc, name) \ argument
36 __raw_readq(&(__dma_regs(dc)->name))
37 #define channel64_writeq(dc, name, val) \ argument
38 __raw_writeq((val), &(__dma_regs(dc)->name))
39 #define channel64_readl(dc, name) \ argument
40 __raw_readl(&(__dma_regs(dc)->name))
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h31 void dcn20_log_color_state(struct dc *dc,
38 struct dc *dc,
41 struct dc *dc,
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
45 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
49 void dcn20_program_output_csc(struct dc *dc,
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
59 struct dc *dc,
[all …]
/linux/drivers/tty/
H A Dnozomi.c315 struct nozomi *dc; member
463 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
465 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
472 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
473 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
474 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
475 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
476 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
477 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
478 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
[all …]
/linux/drivers/md/
H A Ddm-delay.c59 struct delay_c *dc = timer_container_of(dc, t, delay_timer); in handle_delayed_timer() local
61 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
64 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
66 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
69 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
71 return !!dc->worker; in delay_is_fast()
86 static void flush_delayed_bios(struct delay_c *dc, bool flush_all) in flush_delayed_bios() argument
95 mutex_lock(&dc->process_bios_lock); in flush_delayed_bios()
96 spin_lock(&dc->delayed_bios_lock); in flush_delayed_bios()
97 list_replace_init(&dc->delayed_bios, &local_list); in flush_delayed_bios()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.h31 struct dc;
44 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
46 void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
53 bool dcn32_set_input_transfer_func(struct dc *dc,
60 bool dcn32_set_output_transfer_func(struct dc *dc,
64 void dcn32_init_hw(struct dc *dc);
66 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
68 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
70 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_stream.c28 #include "dc.h"
37 #define DC_LOGGER dc->ctx->logger
63 if (stream->ctx->dc->caps.dual_link_dvi && in update_stream_signal()
232 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign && in dc_copy_stream()
233 !new_stream->ctx->dc->config.unify_link_enc_assignment) in dc_copy_stream()
245 * The given stream is expected to exist in dc->current_state. Otherwise, NULL
251 struct dc *dc = stream->ctx->dc; in dc_stream_get_status() local
252 return dc_state_get_stream_status(dc->current_state, stream); in dc_stream_get_status()
258 struct dc *dc = stream->ctx->dc; in dc_stream_get_status_const() local
259 return dc_state_get_stream_status(dc->current_state, stream); in dc_stream_get_status_const()
[all …]
H A Ddc_vm_helper.c27 #include "dc.h"
37 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config) in dc_setup_system_context() argument
42 if (dc->hwss.init_sys_ctx) { in dc_setup_system_context()
43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
48 memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config)); in dc_setup_system_context()
49 dc->vm_pa_config.valid = true; in dc_setup_system_context()
50 dc->dml2_options.gpuvm_enable = true; in dc_setup_system_context()
51 dc_z10_save_init(dc); in dc_setup_system_context()
57 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid) in dc_setup_vm_context() argument
59 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid); in dc_setup_vm_context()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A DMakefile47 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
48 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
49 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
50 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
51 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
52 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
53 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
54 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
55 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) $(frame_warn_flag)
56 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c51 dc->ctx->logger
58 void dcn401_initialize_min_clocks(struct dc *dc) in dcn401_initialize_min_clocks() argument
60 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
63 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
64 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
65 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
66 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn401_initialize_min_clocks()
67 if (dc->debug.disable_boot_optimizations) { in dcn401_initialize_min_clocks()
68 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn401_initialize_min_clocks()
75 if (dc->clk_mgr->funcs->get_dispclk_from_dentist) { in dcn401_initialize_min_clocks()
[all …]
/linux/drivers/gpu/drm/tegra/
H A Ddc.c33 #include "dc.h"
51 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
55 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
56 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
57 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
80 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
88 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
94 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
97 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
99 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
[all …]
/linux/drivers/scsi/esas2r/
H A Desas2r_disc.c291 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_queue_event() local
298 dc->disc_evt |= disc_evt; in esas2r_disc_queue_event()
314 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_start_port() local
326 if (dc->disc_evt) { in esas2r_disc_start_port()
352 esas2r_trace("disc_evt: %d", dc->disc_evt); in esas2r_disc_start_port()
354 dc->flags = 0; in esas2r_disc_start_port()
357 dc->flags |= DCF_POLLED; in esas2r_disc_start_port()
359 rq->interrupt_cx = dc; in esas2r_disc_start_port()
363 if (dc->disc_evt & DCDE_DEV_SCAN) { in esas2r_disc_start_port()
364 dc->disc_evt &= ~DCDE_DEV_SCAN; in esas2r_disc_start_port()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_stream.h105 /* source MPCC instance. for use by internally by dc */
167 * When force_odm_combine_segments is non zero, allow dc to
296 /* Output from DC when stream state is committed or altered
297 * DC may only access these values during:
399 bool dc_update_planes_and_stream(struct dc *dc,
409 struct dc *dc,
441 void dc_commit_updates_for_stream(struct dc *dc,
450 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
452 uint8_t dc_get_current_stream_count(struct dc *dc);
453 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
[all …]
/linux/drivers/clk/mvebu/
H A Ddove-divider.c51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
74 if (dc->divider_table) { in dove_calc_divider()
77 for (i = 0; dc->divider_table[i]; i++) in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.h31 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
39 void dcn20_calculate_dlg_params(struct dc *dc,
44 int dcn20_populate_dml_pipes_from_context(struct dc *dc,
48 void dcn20_calculate_wm(struct dc *dc,
57 void dcn20_update_bounding_box(struct dc *dc,
62 void dcn20_patch_bounding_box(struct dc *dc,
64 bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
75 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
79 bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum
81 void dcn21_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c28 #include "dc.h"
779 ctx->dc->caps.extended_aux_timeout_support); in dcn321_aux_engine_create()
896 ctx->dc->dml.ip.det_buffer_size_kbytes, in dcn321_hubbub_create()
897 ctx->dc->dml.ip.pixel_chunk_size_kbytes, in dcn321_hubbub_create()
898 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); in dcn321_hubbub_create()
1513 struct dc *dc = pool->base.oem_device->ctx->dc; in dcn321_resource_destruct() local
1515 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); in dcn321_resource_destruct()
1529 dm_error("DC: failed to create dwbc30!\n"); in dcn321_dwbc_create()
1557 dm_error("DC: failed to create mcif_wb30!\n"); in dcn321_mmhubbub_create()
1615 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn321_update_bw_bounding_box() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c53 dc->ctx->logger
136 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn201_update_plane_addr() argument
141 struct dce_hwseq *hws = dc->hwseq; in dcn201_update_plane_addr()
168 struct dc *dc, in dcn201_init_blank() argument
171 struct dce_hwseq *hws = dc->hwseq; in dcn201_init_blank()
180 color_space_to_black_color(dc, color_space, &black_color); in dcn201_init_blank()
189 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
190 opp = dc->res_pool->opps[opp_id_src0]; in dcn201_init_blank()
227 void dcn201_init_hw(struct dc *dc) in dcn201_init_hw() argument
230 struct dce_hwseq *hws = dc->hwseq; in dcn201_init_hw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c183 static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct dc_state *context,
189 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn32_build_wm_range_table_fpu()
190 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; in dcn32_build_wm_range_table_fpu()
191 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
192 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn32_build_wm_range_table_fpu()
197 …uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_m… in dcn32_build_wm_range_table_fpu()
235 if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { in dcn32_build_wm_range_table_fpu()
275 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
292 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
293 …dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMIN… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c79 dc->ctx->logger
709 dm_error("DC: failed to create dwbc30!\n"); in dcn303_dwbc_create()
744 dm_error("DC: failed to create mcif_wb30!\n"); in dcn303_mmhubbub_create()
784 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); in dcn303_aux_engine_create()
921 static bool is_soc_bounding_box_valid(struct dc *dc) in is_soc_bounding_box_valid() argument
923 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; in is_soc_bounding_box_valid()
931 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) in init_soc_bounding_box() argument
936 DC_LOGGER_INIT(dc->ctx->logger); in init_soc_bounding_box()
938 if (!is_soc_bounding_box_valid(dc)) { in init_soc_bounding_box()
945 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; in init_soc_bounding_box()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c29 #include "dc.h"
785 ctx->dc->caps.extended_aux_timeout_support); in dcn32_aux_engine_create()
902 ctx->dc->dml.ip.det_buffer_size_kbytes, in dcn32_hubbub_create()
903 ctx->dc->dml.ip.pixel_chunk_size_kbytes, in dcn32_hubbub_create()
904 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); in dcn32_hubbub_create()
1533 struct dc *dc = pool->base.oem_device->ctx->dc; in dcn32_resource_destruct() local
1535 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); in dcn32_resource_destruct()
1549 dm_error("DC: failed to create dwbc30!\n"); in dcn32_dwbc_create()
1577 dm_error("DC: failed to create mcif_wb30!\n"); in dcn32_mmhubbub_create()
1674 static void dcn32_enable_phantom_plane(struct dc *dc, in dcn32_enable_phantom_plane() argument
[all …]
/linux/drivers/md/bcache/
H A Dwriteback.h78 static inline bool bcache_dev_stripe_dirty(struct cached_dev *dc, in bcache_dev_stripe_dirty() argument
82 int stripe = offset_to_stripe(&dc->disk, offset); in bcache_dev_stripe_dirty()
88 if (atomic_read(dc->disk.stripe_sectors_dirty + stripe)) in bcache_dev_stripe_dirty()
91 if (nr_sectors <= dc->disk.stripe_size) in bcache_dev_stripe_dirty()
94 nr_sectors -= dc->disk.stripe_size; in bcache_dev_stripe_dirty()
102 static inline bool should_writeback(struct cached_dev *dc, struct bio *bio, in should_writeback() argument
105 unsigned int in_use = dc->disk.c->gc_stats.in_use; in should_writeback()
108 test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) || in should_writeback()
115 if (dc->partial_stripes_expensive && in should_writeback()
116 bcache_dev_stripe_dirty(dc, bio->bi_iter.bi_sector, in should_writeback()
[all …]

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