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/linux/arch/m68k/ifpsp060/
H A Dpfpsp.sa1 dc.l $60ff0000,$17400000,$60ff0000,$15f40000
2 dc.l $60ff0000,$02b60000,$60ff0000,$04700000
3 dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000
4 dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000
5 dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f
10 dc.l $00044e74,$00042f00,$203afef2,$487b0930
[all …]
H A Dfplsp.sa1 dc.l $60ff0000,$238e0000,$60ff0000,$24200000
2 dc.l $60ff0000,$24b60000,$60ff0000,$11060000
3 dc.l $60ff0000,$11980000,$60ff0000,$122e0000
4 dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000
5 dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000
6 dc.l $60ff0000,$13400000,$60ff0000,$13d60000
7 dc.l $60ff0000,$05ae0000,$60ff0000,$06400000
8 dc.l $60ff0000,$06d60000,$60ff0000,$213e0000
9 dc.l $60ff0000,$21d00000,$60ff0000,$22660000
10 dc.l $60ff0000,$16160000,$60ff0000,$16a80000
[all …]
H A Ditest.sa1 dc.l $60ff0000,$005c5465,$7374696e,$67203638
2 dc.l $30363020,$49535020,$73746172,$7465643a
3 dc.l $0a007061,$73736564,$0a002066,$61696c65
4 dc.l $640a0000,$4a80660e,$487affe8,$61ff0000
5 dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f
6 dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56
7 dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c
8 dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff
9 dc.l $00004f58,$588f61ff,$000000f0,$61ffffff
10 dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff
[all …]
H A Dftest.sa1 dc.l $60ff0000,$00d40000,$60ff0000,$016c0000
2 dc.l $60ff0000,$01a80000,$54657374,$696e6720
3 dc.l $36383036,$30204650,$53502073,$74617274
4 dc.l $65643a0a,$00546573,$74696e67,$20363830
5 dc.l $36302046,$50535020,$756e696d,$706c656d
6 dc.l $656e7465,$6420696e,$73747275,$6374696f
7 dc.l $6e207374,$61727465,$643a0a00,$54657374
8 dc.l $696e6720,$36383036,$30204650,$53502065
9 dc.l $78636570,$74696f6e,$20656e61,$626c6564
10 dc.l $20737461,$72746564,$3a0a0070,$61737365
[all …]
H A Dilsp.sa1 dc.l $60ff0000,$01fe0000,$60ff0000,$02080000
2 dc.l $60ff0000,$04900000,$60ff0000,$04080000
3 dc.l $60ff0000,$051e0000,$60ff0000,$053c0000
4 dc.l $60ff0000,$055a0000,$60ff0000,$05740000
5 dc.l $60ff0000,$05940000,$60ff0000,$05b40000
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
10 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h31 void dcn20_log_color_state(struct dc *dc,
38 struct dc *dc,
41 struct dc *dc,
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
45 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
49 void dcn20_program_output_csc(struct dc *dc,
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
59 struct dc *dc,
[all …]
/linux/drivers/tty/
H A Dnozomi.c315 struct nozomi *dc; member
463 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
465 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
472 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
473 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
474 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
475 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
476 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
477 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
478 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c29 #include "dc.h"
90 dc->ctx
93 dc->ctx->logger
100 * DC is the OS-agnostic component of the amdgpu DC driver.
102 * DC maintains and validates a set of structs representing the state of the
105 * Main DC HW structs:
107 * struct dc - The central struct. One per driver. Created on driver load,
111 * Used as a backpointer by most other structs in dc.
124 * Main dc state structs:
127 * these structs in dc->current_state representing the currently programmed state.
[all …]
H A Ddc_state.c42 dc->ctx->logger
183 static void init_state(struct dc *dc, struct dc_state *state) in init_state() argument
186 * initialize and obtain IP and SOC the base DML instance from DC is in init_state()
189 memcpy(&state->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); in init_state()
193 struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params) in dc_state_create() argument
197 struct dml2_configuration_options *dml2_opt = &dc->dml2_tmp; in dc_state_create()
199 memcpy(dml2_opt, &dc->dml2_options, sizeof(dc->dml2_options)); in dc_state_create()
207 init_state(dc, state); in dc_state_create()
208 dc_state_construct(dc, state); in dc_state_create()
212 if (dc->debug.using_dml2) { in dc_state_create()
[all …]
/linux/drivers/md/
H A Ddm-delay.c55 struct delay_c *dc = from_timer(dc, t, delay_timer); in handle_delayed_timer() local
57 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
60 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
62 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
65 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
67 return !!dc->worker; in delay_is_fast()
82 static void flush_delayed_bios(struct delay_c *dc, bool flush_all) in flush_delayed_bios() argument
91 mutex_lock(&dc->process_bios_lock); in flush_delayed_bios()
92 spin_lock(&dc->delayed_bios_lock); in flush_delayed_bios()
93 list_replace_init(&dc->delayed_bios, &local_list); in flush_delayed_bios()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer_private.h75 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
76 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
77 void (*init_pipes)(struct dc *dc, struct dc_state *context);
78 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
79 void (*plane_atomic_disconnect)(struct dc *dc,
82 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
83 bool (*set_input_transfer_func)(struct dc *dc,
86 bool (*set_output_transfer_func)(struct dc *dc,
89 void (*power_down)(struct dc *dc);
92 bool (*enable_display_power_gating)(struct dc *dc,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.h31 struct dc;
44 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
46 void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
53 bool dcn32_set_input_transfer_func(struct dc *dc,
60 bool dcn32_set_output_transfer_func(struct dc *dc,
64 void dcn32_init_hw(struct dc *dc);
66 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
68 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
70 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c76 static void enable_memory_low_power(struct dc *dc)
78 struct dce_hwseq *hws = dc->hwseq;
81 if (dc->debug.enable_mem_low_power.bits.dmcu) {
83 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
89 if (dc->debug.enable_mem_low_power.bits.optc) {
94 if (dc->debug.enable_mem_low_power.bits.vga) {
99 if (dc->debug.enable_mem_low_power.bits.mpc &&
100 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)
101 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
103 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd…
[all …]
H A Ddcn35_hwseq.h32 struct dc;
34 void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
48 void dcn35_init_hw(struct dc *dc);
54 void dcn35_power_down_on_boot(struct dc *dc);
56 bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
58 void dcn35_z10_restore(const struct dc *dc);
60 void dcn35_init_pipes(struct dc *dc, struct dc_state *context);
61 void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
62 void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
64 void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A DMakefile43 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
44 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
45 CFLAGS_$(AMDDALPATH)/dc/dml/dcn10/dcn10_fpu.o := $(dml_ccflags)
46 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
47 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags) $(frame_warn_flag)
48 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
49 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) $(frame_warn_flag)
50 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
51 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) $(frame_warn_flag)
52 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn401/
H A Ddcn401_fpu.c16 double pstate_latency_us = clk_mgr->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn401_build_wm_range_table_fpu()
17 double fclk_change_latency_us = clk_mgr->ctx->dc->dml.soc.fclk_change_latency_us; in dcn401_build_wm_range_table_fpu()
18 double sr_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_exit_time_us; in dcn401_build_wm_range_table_fpu()
19 double sr_enter_plus_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn401_build_wm_range_table_fpu()
24 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
62 if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { in dcn401_build_wm_range_table_fpu()
101 * - with passed few options from dc->config
104 * - with passed latency values (passed in ns units) in dc-> bb override for
114 void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) in dcn401_update_bw_bounding_box_fpu() argument
118 /* Override from passed dc->bb_overrides if available*/ in dcn401_update_bw_bounding_box_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c28 #include "dc.h"
40 dc->ctx->logger
318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
453 const struct dc *dc, in dcn_bw_calc_rq_dlg_ttu() argument
458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu()
497 input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu()
500 // dc->dml.logger = pool->base.logger; in dcn_bw_calc_rq_dlg_ttu()
638 static bool dcn_bw_apply_registry_override(struct dc *dc) in dcn_bw_apply_registry_override() argument
642 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns in dcn_bw_apply_registry_override()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A DMakefile46 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2
47 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_core
48 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_mcg/
49 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_dpmm/
50 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_pmo/
51 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_standalone_libraries/
52 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/inc
53 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/inc
54 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/
56 CFLAGS_$(AMDDALPATH)/dc/dml2/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c65 dc->ctx->logger
72 void dcn30_log_color_state(struct dc *dc, in dcn30_log_color_state() argument
75 struct dc_context *dc_ctx = dc->ctx; in dcn30_log_color_state()
76 struct resource_pool *pool = dc->res_pool; in dcn30_log_color_state()
147 dc->caps.color.dpp.input_lut_shared, in dcn30_log_color_state()
148 dc->caps.color.dpp.icsc, in dcn30_log_color_state()
149 dc->caps.color.dpp.dgam_ram, in dcn30_log_color_state()
150 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn30_log_color_state()
151 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn30_log_color_state()
152 dc->caps.color.dpp.dgam_rom_caps.gamma2_2, in dcn30_log_color_state()
[all …]
/linux/drivers/scsi/esas2r/
H A Desas2r_disc.c291 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_queue_event() local
298 dc->disc_evt |= disc_evt; in esas2r_disc_queue_event()
314 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_start_port() local
326 if (dc->disc_evt) { in esas2r_disc_start_port()
352 esas2r_trace("disc_evt: %d", dc->disc_evt); in esas2r_disc_start_port()
354 dc->flags = 0; in esas2r_disc_start_port()
357 dc->flags |= DCF_POLLED; in esas2r_disc_start_port()
359 rq->interrupt_cx = dc; in esas2r_disc_start_port()
363 if (dc->disc_evt & DCDE_DEV_SCAN) { in esas2r_disc_start_port()
364 dc->disc_evt &= ~DCDE_DEV_SCAN; in esas2r_disc_start_port()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.h34 struct dc;
46 struct dc *dc);
49 struct dc *dc,
59 bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
62 struct dc *dc,
70 struct dc *dc, struct dc_state *context,
74 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
76 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
79 struct dc *dc, struct dc_state *context,
97 struct dc *dc,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_state_priv.h47 struct dc_stream_state *dc_state_create_phantom_stream(const struct dc *dc,
50 struct dc_plane_state *dc_state_create_phantom_plane(const struct dc *dc,
55 void dc_state_release_phantom_stream(const struct dc *dc,
58 void dc_state_release_phantom_plane(const struct dc *dc,
63 enum dc_status dc_state_add_phantom_stream(const struct dc *dc,
67 enum dc_status dc_state_remove_phantom_stream(const struct dc *dc,
72 const struct dc *dc,
78 const struct dc *dc,
84 const struct dc *dc,
90 const struct dc *dc,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.h35 struct dc;
50 struct dc *dc);
76 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
118 struct dc *dc,
122 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
124 struct dc *dc,
127 struct dc *dc,
135 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
142 const struct dc *dc,
146 void dcn20_acquire_dsc(const struct dc *dc,
[all …]
/linux/drivers/clk/mvebu/
H A Ddove-divider.c51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
74 if (dc->divider_table) { in dove_calc_divider()
77 for (i = 0; dc->divider_table[i]; i++) in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.h31 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
39 void dcn20_calculate_dlg_params(struct dc *dc,
44 int dcn20_populate_dml_pipes_from_context(struct dc *dc,
48 void dcn20_calculate_wm(struct dc *dc,
57 void dcn20_update_bounding_box(struct dc *dc,
62 void dcn20_patch_bounding_box(struct dc *dc,
64 bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
75 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
79 bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool
81 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
[all …]

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