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/linux/arch/m68k/ifpsp060/
H A Dpfpsp.sa1 dc.l $60ff0000,$17400000,$60ff0000,$15f40000
2 dc.l $60ff0000,$02b60000,$60ff0000,$04700000
3 dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000
4 dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000
5 dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f
10 dc.l $00044e74,$00042f00,$203afef2,$487b0930
[all …]
H A Dfplsp.sa1 dc.l $60ff0000,$238e0000,$60ff0000,$24200000
2 dc.l $60ff0000,$24b60000,$60ff0000,$11060000
3 dc.l $60ff0000,$11980000,$60ff0000,$122e0000
4 dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000
5 dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000
6 dc.l $60ff0000,$13400000,$60ff0000,$13d60000
7 dc.l $60ff0000,$05ae0000,$60ff0000,$06400000
8 dc.l $60ff0000,$06d60000,$60ff0000,$213e0000
9 dc.l $60ff0000,$21d00000,$60ff0000,$22660000
10 dc.l $60ff0000,$16160000,$60ff0000,$16a80000
[all …]
H A Ditest.sa1 dc.l $60ff0000,$005c5465,$7374696e,$67203638
2 dc.l $30363020,$49535020,$73746172,$7465643a
3 dc.l $0a007061,$73736564,$0a002066,$61696c65
4 dc.l $640a0000,$4a80660e,$487affe8,$61ff0000
5 dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f
6 dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56
7 dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c
8 dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff
9 dc.l $00004f58,$588f61ff,$000000f0,$61ffffff
10 dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff
[all …]
H A Dftest.sa1 dc.l $60ff0000,$00d40000,$60ff0000,$016c0000
2 dc.l $60ff0000,$01a80000,$54657374,$696e6720
3 dc.l $36383036,$30204650,$53502073,$74617274
4 dc.l $65643a0a,$00546573,$74696e67,$20363830
5 dc.l $36302046,$50535020,$756e696d,$706c656d
6 dc.l $656e7465,$6420696e,$73747275,$6374696f
7 dc.l $6e207374,$61727465,$643a0a00,$54657374
8 dc.l $696e6720,$36383036,$30204650,$53502065
9 dc.l $78636570,$74696f6e,$20656e61,$626c6564
10 dc.l $20737461,$72746564,$3a0a0070,$61737365
[all …]
H A Dilsp.sa1 dc.l $60ff0000,$01fe0000,$60ff0000,$02080000
2 dc.l $60ff0000,$04900000,$60ff0000,$04080000
3 dc.l $60ff0000,$051e0000,$60ff0000,$053c0000
4 dc.l $60ff0000,$055a0000,$60ff0000,$05740000
5 dc.l $60ff0000,$05940000,$60ff0000,$05b40000
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
10 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
[all …]
/linux/drivers/tty/
H A Dnozomi.c315 struct nozomi *dc; member
463 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
465 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
472 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
473 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
474 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
475 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
476 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
477 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
478 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h31 void dcn20_log_color_state(struct dc *dc,
38 struct dc *dc,
41 struct dc *dc,
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
45 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
49 void dcn20_program_output_csc(struct dc *dc,
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
59 struct dc *dc,
[all …]
H A Ddcn20_hwseq.c74 void dcn20_log_color_state(struct dc *dc, in dcn20_log_color_state() argument
77 struct dc_context *dc_ctx = dc->ctx; in dcn20_log_color_state()
78 struct resource_pool *pool = dc->res_pool; in dcn20_log_color_state()
150 dc->caps.color.dpp.input_lut_shared, in dcn20_log_color_state()
151 dc->caps.color.dpp.icsc, in dcn20_log_color_state()
152 dc->caps.color.dpp.dgam_ram, in dcn20_log_color_state()
153 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn20_log_color_state()
154 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn20_log_color_state()
155 dc->caps.color.dpp.dgam_rom_caps.gamma2_2, in dcn20_log_color_state()
156 dc->caps.color.dpp.dgam_rom_caps.pq, in dcn20_log_color_state()
[all …]
/linux/drivers/md/
H A Ddm-delay.c59 struct delay_c *dc = timer_container_of(dc, t, delay_timer); in handle_delayed_timer() local
61 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
64 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
66 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
69 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
71 return !!dc->worker; in delay_is_fast()
86 static void flush_delayed_bios(struct delay_c *dc, bool flush_all) in flush_delayed_bios() argument
95 mutex_lock(&dc->process_bios_lock); in flush_delayed_bios()
96 spin_lock(&dc->delayed_bios_lock); in flush_delayed_bios()
97 list_replace_init(&dc->delayed_bios, &local_list); in flush_delayed_bios()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h57 struct dc *dc; member
63 struct dc *dc; member
74 const struct dc *dc; member
80 struct dc *dc; member
85 struct dc *dc; member
113 struct dc *dc; member
119 struct dc *dc; member
151 const struct dc *dc; member
156 struct dc *dc; member
178 struct dc *dc; member
[all …]
H A Dhw_sequencer_private.h77 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
78 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
79 void (*init_pipes)(struct dc *dc, struct dc_state *context);
80 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
81 void (*plane_atomic_disconnect)(struct dc *dc,
[all...]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.h9 #include "dc.h"
15 struct dc;
37 void dcn401_init_hw(struct dc *dc);
41 bool dcn401_set_output_transfer_func(struct dc *dc,
44 void dcn401_trigger_3dlut_dma_load(struct dc *dc,
51 struct dc *dc);
[all...]
H A Ddcn401_hwseq.c50 dc->ctx->logger
57 void dcn401_initialize_min_clocks(struct dc *dc) in dcn401_initialize_min_clocks() argument
59 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
62 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
63 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
64 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
65 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn401_initialize_min_clocks()
66 if (dc->debug.disable_boot_optimizations) { in dcn401_initialize_min_clocks()
67 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn401_initialize_min_clocks()
74 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); in dcn401_initialize_min_clocks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c29 #include "dc.h"
93 dc->ctx
96 dc->ctx->logger
103 * DC is the OS-agnostic component of the amdgpu DC driver.
105 * DC maintains and validates a set of structs representing the state of the
108 * Main DC HW structs:
110 * struct dc - The central struct. One per driver. Created on driver load,
114 * Used as a backpointer by most other structs in dc.
127 * Main dc state structs:
130 * these structs in dc->current_state representing the currently programmed state.
[all …]
H A Ddc_stream.c28 #include "dc.h"
37 #define DC_LOGGER dc->ctx->logger
56 if (stream->ctx->dc->caps.dual_link_dvi && in update_stream_signal()
204 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign && in dc_copy_stream()
205 !new_stream->ctx->dc->config.unify_link_enc_assignment) in dc_copy_stream()
217 * The given stream is expected to exist in dc->current_state. Otherwise, NULL
223 struct dc *dc = stream->ctx->dc; in dc_stream_get_status() local
224 return dc_state_get_stream_status(dc->current_state, stream); in dc_stream_get_status()
230 struct dc *dc = stream->ctx->dc; in dc_stream_get_status_const() local
232 return dc_state_get_stream_status(dc->current_state, stream); in dc_stream_get_status_const()
[all …]
H A Ddc_vm_helper.c27 #include "dc.h"
37 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config) in dc_setup_system_context() argument
42 if (dc->hwss.init_sys_ctx) { in dc_setup_system_context()
43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
48 memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config)); in dc_setup_system_context()
49 dc->vm_pa_config.valid = true; in dc_setup_system_context()
50 dc->dml2_options.gpuvm_enable = true; in dc_setup_system_context()
51 dc_z10_save_init(dc); in dc_setup_system_context()
57 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid) in dc_setup_vm_context() argument
59 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid); in dc_setup_vm_context()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c76 static void enable_memory_low_power(struct dc *dc)
78 struct dce_hwseq *hws = dc->hwseq;
81 if (dc->debug.enable_mem_low_power.bits.dmcu) {
83 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
89 if (dc->debug.enable_mem_low_power.bits.optc) {
94 if (dc->debug.enable_mem_low_power.bits.vga) {
99 if (dc->debug.enable_mem_low_power.bits.mpc &&
100 dc
116 print_pg_status(struct dc * dc,const char * debug_func,const char * debug_log) print_pg_status() argument
138 dcn35_init_hw(struct dc * dc) dcn35_init_hw() argument
428 dcn35_update_odm(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx) dcn35_update_odm() argument
518 dcn35_power_down_on_boot(struct dc * dc) dcn35_power_down_on_boot() argument
563 dcn35_apply_idle_power_optimizations(struct dc * dc,bool enable) dcn35_apply_idle_power_optimizations() argument
610 dcn35_z10_restore(const struct dc * dc) dcn35_z10_restore() argument
620 dcn35_init_pipes(struct dc * dc,struct dc_state * context) dcn35_init_pipes() argument
815 dcn35_enable_plane(struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_state * context) dcn35_enable_plane() argument
858 dcn35_plane_atomic_disable(struct dc * dc,struct pipe_ctx * pipe_ctx) dcn35_plane_atomic_disable() argument
898 dcn35_disable_plane(struct dc * dc,struct dc_state * state,struct pipe_ctx * pipe_ctx) dcn35_disable_plane() argument
922 dcn35_calc_blocks_to_gate(struct dc * dc,struct dc_state * context,struct pg_block_update * update_state) dcn35_calc_blocks_to_gate() argument
1026 dcn35_calc_blocks_to_ungate(struct dc * dc,struct dc_state * context,struct pg_block_update * update_state) dcn35_calc_blocks_to_ungate() argument
1180 dcn35_hw_block_power_down(struct dc * dc,struct pg_block_update * update_state) dcn35_hw_block_power_down() argument
1257 dcn35_hw_block_power_up(struct dc * dc,struct pg_block_update * update_state) dcn35_hw_block_power_up() argument
1299 dcn35_root_clock_control(struct dc * dc,struct pg_block_update * update_state,bool power_on) dcn35_root_clock_control() argument
1359 dcn35_prepare_bandwidth(struct dc * dc,struct dc_state * context) dcn35_prepare_bandwidth() argument
1380 dcn35_optimize_bandwidth(struct dc * dc,struct dc_state * context) dcn35_optimize_bandwidth() argument
1427 struct dc *dc = pipe_ctx[i]->stream->ctx->dc; dcn35_set_drr() local
1504 const struct dc *dc = pipe_ctx->stream->link->dc; should_avoid_empty_tu() local
1547 struct dc *dc = pipe_ctx->stream->ctx->dc; dcn35_is_dp_dig_pixel_rate_div_policy() local
1565 dcn35_calc_blocks_to_ungate_for_hw_release(struct dc * dc,struct pg_block_update * update_state) dcn35_calc_blocks_to_ungate_for_hw_release() argument
1583 dcn35_hardware_release(struct dc * dc) dcn35_hardware_release() argument
[all...]
H A Ddcn35_hwseq.h32 struct dc;
34 void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
48 void dcn35_init_hw(struct dc *dc);
54 void dcn35_power_down_on_boot(struct dc *dc);
56 bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
58 void dcn35_z10_restore(const struct dc *d
[all...]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.h31 struct dc;
44 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
46 void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
53 bool dcn32_set_input_transfer_func(struct dc *dc,
60 bool dcn32_set_output_transfer_func(struct dc *dc,
64 void dcn32_init_hw(struct dc *dc);
66 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
68 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
70 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);
[all …]
/linux/drivers/gpu/drm/tegra/
H A Ddc.c33 #include "dc.h"
51 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active()
55 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
56 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
57 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
80 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
88 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
94 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
97 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output()
99 struct device_node *np = dc in tegra_dc_has_output()
50 tegra_dc_readl_active(struct tegra_dc * dc,unsigned long offset) tegra_dc_readl_active() argument
96 tegra_dc_has_output(struct tegra_dc * dc,struct device * dev) tegra_dc_has_output() argument
121 tegra_dc_commit(struct tegra_dc * dc) tegra_dc_commit() argument
317 struct tegra_dc *dc = plane->dc; tegra_plane_use_horizontal_filtering() local
332 struct tegra_dc *dc = plane->dc; tegra_plane_use_vertical_filtering() local
350 struct tegra_dc *dc = plane->dc; tegra_dc_setup_window() local
629 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); tegra_plane_atomic_check() local
804 tegra_primary_plane_create(struct drm_device * drm,struct tegra_dc * dc) tegra_primary_plane_create() argument
907 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); __tegra_cursor_atomic_update() local
1014 struct tegra_dc *dc; tegra_cursor_atomic_disable() local
1070 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); tegra_cursor_atomic_async_update() local
1109 tegra_dc_cursor_plane_create(struct drm_device * drm,struct tegra_dc * dc) tegra_dc_cursor_plane_create() argument
1254 tegra_dc_overlay_plane_create(struct drm_device * drm,struct tegra_dc * dc,unsigned int index,bool cursor) tegra_dc_overlay_plane_create() argument
1313 tegra_dc_add_shared_planes(struct drm_device * drm,struct tegra_dc * dc) tegra_dc_add_shared_planes() argument
1351 tegra_dc_add_planes(struct drm_device * drm,struct tegra_dc * dc) tegra_dc_add_planes() argument
1648 struct tegra_dc *dc = node->info_ent->data; tegra_dc_show_regs() local
1674 struct tegra_dc *dc = node->info_ent->data; tegra_dc_show_crc() local
1705 struct tegra_dc *dc = node->info_ent->data; tegra_dc_show_stats() local
1731 struct tegra_dc *dc = to_tegra_dc(crtc); tegra_dc_late_register() local
1756 struct tegra_dc *dc = to_tegra_dc(crtc); tegra_dc_early_unregister() local
1772 struct tegra_dc *dc = to_tegra_dc(crtc); tegra_dc_get_vblank_counter() local
1784 struct tegra_dc *dc = to_tegra_dc(crtc); tegra_dc_enable_vblank() local
1796 struct tegra_dc *dc = to_tegra_dc(crtc); tegra_dc_disable_vblank() local
1818 tegra_dc_set_timings(struct tegra_dc * dc,struct drm_display_mode * mode) tegra_dc_set_timings() argument
1862 tegra_dc_state_setup_clock(struct tegra_dc * dc,struct drm_crtc_state * crtc_state,struct clk * clk,unsigned long pclk,unsigned int div) tegra_dc_state_setup_clock() argument
1879 tegra_dc_update_voltage_state(struct tegra_dc * dc,struct tegra_dc_state * state) tegra_dc_update_voltage_state() argument
1925 tegra_dc_set_clock_rate(struct tegra_dc * dc,struct tegra_dc_state * state) tegra_dc_set_clock_rate() argument
1962 tegra_dc_stop(struct tegra_dc * dc) tegra_dc_stop() argument
1974 tegra_dc_idle(struct tegra_dc * dc) tegra_dc_idle() argument
1983 tegra_dc_wait_idle(struct tegra_dc * dc,unsigned long timeout) tegra_dc_wait_idle() argument
2008 struct tegra_dc *dc = to_tegra_dc(crtc); tegra_crtc_update_memory_bandwidth() local
2098 struct tegra_dc *dc = to_tegra_dc(crtc); tegra_crtc_atomic_disable() local
2164 struct tegra_dc *dc = to_tegra_dc(crtc); tegra_crtc_atomic_enable() local
2317 struct tegra_dc *dc = to_tegra_dc(crtc); tegra_crtc_atomic_flush() local
2399 struct tegra_dc *dc = to_tegra_dc(crtc); tegra_crtc_calculate_memory_bandwidth() local
2536 struct tegra_dc *dc = data; tegra_dc_irq() local
2584 tegra_dc_has_window_groups(struct tegra_dc * dc) tegra_dc_has_window_groups() argument
2615 struct tegra_dc *dc = host1x_client_to_dc(client); tegra_dc_init() local
2736 struct tegra_dc *dc = host1x_client_to_dc(client); tegra_dc_exit() local
2771 struct tegra_dc *dc = host1x_client_to_dc(client); tegra_dc_runtime_suspend() local
2792 struct tegra_dc *dc = host1x_client_to_dc(client); tegra_dc_runtime_resume() local
3086 tegra_dc_parse_dt(struct tegra_dc * dc) tegra_dc_parse_dt() argument
3125 struct tegra_dc *dc = dev_get_drvdata(dev); tegra_dc_match_by_pipe() local
3131 tegra_dc_couple(struct tegra_dc * dc) tegra_dc_couple() argument
3157 tegra_dc_init_opp_table(struct tegra_dc * dc) tegra_dc_init_opp_table() argument
3177 struct tegra_dc *dc; tegra_dc_probe() local
3283 struct tegra_dc *dc = platform_get_drvdata(pdev); tegra_dc_remove() local
[all...]
/linux/drivers/scsi/esas2r/
H A Desas2r_disc.c291 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_queue_event() local
298 dc->disc_evt |= disc_evt; in esas2r_disc_queue_event()
314 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_start_port() local
326 if (dc->disc_evt) { in esas2r_disc_start_port()
352 esas2r_trace("disc_evt: %d", dc->disc_evt); in esas2r_disc_start_port()
354 dc->flags = 0; in esas2r_disc_start_port()
357 dc->flags |= DCF_POLLED; in esas2r_disc_start_port()
359 rq->interrupt_cx = dc; in esas2r_disc_start_port()
363 if (dc->disc_evt & DCDE_DEV_SCAN) { in esas2r_disc_start_port()
364 dc->disc_evt &= ~DCDE_DEV_SCAN; in esas2r_disc_start_port()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c27 #include "dc.h"
90 struct dc_context *ctx = dc->ctx
207 struct dc *dc, in dce110_enable_display_power_gating() argument
214 struct dc_context *ctx = dc->ctx; in dce110_enable_display_power_gating()
215 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
283 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_input_transfer_func() argument
606 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_output_transfer_func() argument
682 const struct dc *dc = link->dc; in dce110_enable_stream() local
690 dc->hwss.update_info_frame(pipe_ctx); in dce110_enable_stream()
757 hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); in dce110_edp_wait_for_hpd_ready()
[all …]
/linux/drivers/clk/mvebu/
H A Ddove-divider.c51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
74 if (dc->divider_table) { in dove_calc_divider()
77 for (i = 0; dc->divider_table[i]; i++) in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
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/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_edp_panel_control.c38 #include "dc/dc_dmub_srv.h"
169 !link->dc->caps.dmub_caps.aux_backlight_support) { in edp_set_backlight_level_nits()
403 link->dc->hwss.edp_power_control(link, true); in edp_panel_backlight_power_on()
405 link->dc->hwss.edp_wait_for_hpd_ready(link, true); in edp_panel_backlight_power_on()
406 if (link->dc->hwss.edp_backlight_control) in edp_panel_backlight_power_on()
407 link->dc->hwss.edp_backlight_control(link, true); in edp_panel_backlight_power_on()
414 if (!link->dc->config.edp_no_power_sequencing) in edp_set_panel_power()
415 link->dc->hwss.edp_power_control(link, true); in edp_set_panel_power()
416 link->dc->hwss.edp_wait_for_hpd_ready(link, true); in edp_set_panel_power()
419 if (link->dc->hwss.edp_backlight_control) in edp_set_panel_power()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource_helpers.c40 struct dc *dc, in dcn32_helper_calculate_mall_bytes_for_cursor() argument
85 * @dc: current dc state
86 * @context: new dc state
91 struct dc *dc, in dcn32_helper_calculate_num_ways_for_subvp() argument
95 if (dc->debug.force_subvp_num_ways) { in dcn32_helper_calculate_num_ways_for_subvp()
96 return dc->debug.force_subvp_num_ways; in dcn32_helper_calculate_num_ways_for_subvp()
97 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { in dcn32_helper_calculate_num_ways_for_subvp()
98 …return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_s… in dcn32_helper_calculate_num_ways_for_subvp()
107 void dcn32_merge_pipes_for_subvp(struct dc *dc, in dcn32_merge_pipes_for_subvp() argument
113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
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